[PATCH] D97133: [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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This also removes a pattern from RISCV that is no longer needed
since the sexti32 on the LHS of the srem in the pattern implies
the result is sign extended so the sign_extend_inreg should be
removed in DAG combine now.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97133

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoM.td
  llvm/test/CodeGen/Mips/llvm-ir/srem.ll
  llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

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