[PATCH] D97130: [RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:403
 // [u]int->fp. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp (i64 (sexti32 GPR:$rs1))), (FCVT_S_W $rs1, 0b111)>;
+def : Pat<(sint_to_fp (i64 (sexti32 i64:$rs1))), (FCVT_S_W $rs1, 0b111)>;
 def : Pat<(uint_to_fp (i64 (zexti32 GPR:$rs1))), (FCVT_S_WU $rs1, 0b111)>;
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The i64 instead of GPR here tricks tablegen into not generating extra patterns for RV32.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97130/new/

https://reviews.llvm.org/D97130