[llvm] 9aa20ca - [RISCV] Improve register allocation around vector masks

[Fraser Cormack via llvm-commits]

Author: Fraser Cormack
Date: 2021-02-20T14:47:51Z
New Revision: 9aa20caee6b47ac601602c674749fb6c1d2179cf

URL: https://github.com/llvm/llvm-project/commit/9aa20caee6b47ac601602c674749fb6c1d2179cf
DIFF: https://github.com/llvm/llvm-project/commit/9aa20caee6b47ac601602c674749fb6c1d2179cf.diff

LOG: [RISCV] Improve register allocation around vector masks

With vector mask registers only allocatable to V0 (VMV0Regs) it is
relatively simple to generate code which uses multiple masks and naively
requires spilling.

This patch aims to improve codegen in such cases by telling LLVM it can
use VRRegs to hold masks. This will prevent spilling in many cases by
having LLVM copy to an available VR register.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D97055

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 2f86164b6247..e1cd29c49158 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -296,3 +296,11 @@ RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
     return CSR_ILP32D_LP64D_RegMask;
   }
 }
+
+const TargetRegisterClass *
+RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
+                                             const MachineFunction &) const {
+  if (RC == &RISCV::VMV0RegClass)
+    return &RISCV::VRRegClass;
+  return RC;
+}

diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index ffbb60abf755..74a5b83ff6f3 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -59,6 +59,10 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
                      unsigned Kind = 0) const override {
     return &RISCV::GPRRegClass;
   }
+
+  const TargetRegisterClass *
+  getLargestLegalSuperClass(const TargetRegisterClass *RC,
+                            const MachineFunction &) const override;
 };
 }
 

diff  --git a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
index ce621670590b..4621a8bfaba0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
@@ -15,24 +15,10 @@ body:             |
     liveins: $v0, $v1, $v2, $v3
     ; CHECK-LABEL: name: mask_reg_alloc
     ; CHECK: liveins: $v0, $v1, $v2, $v3
-    ; CHECK: CFI_INSTRUCTION def_cfa_offset 0
-    ; CHECK: $x10 = PseudoReadVLENB
-    ; CHECK: $x10 = SLLI killed $x10, 1
-    ; CHECK: $x2 = SUB $x2, killed $x10
-    ; CHECK: PseudoVSPILL_M1 $v0, $x2 :: (store unknown-size into %stack.1, align 8)
-    ; CHECK: $x10 = PseudoReadVLENB
-    ; CHECK: $x10 = ADD $x2, killed $x10
-    ; CHECK: PseudoVSPILL_M1 $v1, killed $x10 :: (store unknown-size into %stack.0, align 8)
-    ; CHECK: renamable $v0 = PseudoVRELOAD_M1 $x2 :: (load unknown-size from %stack.1, align 8)
     ; CHECK: renamable $v25 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, $noreg, -1, implicit $vl, implicit $vtype
-    ; CHECK: $x10 = PseudoReadVLENB
-    ; CHECK: $x10 = ADD $x2, killed $x10
-    ; CHECK: renamable $v0 = PseudoVRELOAD_M1 killed $x10 :: (load unknown-size from %stack.0, align 8)
+    ; CHECK: renamable $v0 = COPY killed renamable $v1
     ; CHECK: renamable $v26 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, $noreg, -1, implicit $vl, implicit $vtype
     ; CHECK: renamable $v0 = PseudoVADD_VV_M1 killed renamable $v25, killed renamable $v26, $noreg, -1, implicit $vl, implicit $vtype
-    ; CHECK: $x10 = PseudoReadVLENB
-    ; CHECK: $x10 = SLLI killed $x10, 1
-    ; CHECK: $x2 = ADD $x2, killed $x10
     ; CHECK: PseudoRET implicit $v0
     %0:vr = COPY $v0
     %1:vr = COPY $v1