[llvm] 55b75d8 - [RISCV] Pre-commit test case for D97055. NFC.

[Fraser Cormack via llvm-commits]

Author: Fraser Cormack
Date: 2021-02-20T12:36:55Z
New Revision: 55b75d83637d57d542be483645487d254db345af

URL: https://github.com/llvm/llvm-project/commit/55b75d83637d57d542be483645487d254db345af
DIFF: https://github.com/llvm/llvm-project/commit/55b75d83637d57d542be483645487d254db345af.diff

LOG: [RISCV] Pre-commit test case for D97055. NFC.

This adds a test which unnecessarily spills mask registers.

Added: 
    llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
new file mode 100644
index 000000000000..ce621670590b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+# RUN:     -start-after finalize-isel -stop-after prologepilog -o - %s | FileCheck %s
+
+--- |
+  define void @mask_reg_alloc() {
+    ret void
+  }
+...
+---
+name: mask_reg_alloc
+tracksRegLiveness: true
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $v0, $v1, $v2, $v3
+    ; CHECK-LABEL: name: mask_reg_alloc
+    ; CHECK: liveins: $v0, $v1, $v2, $v3
+    ; CHECK: CFI_INSTRUCTION def_cfa_offset 0
+    ; CHECK: $x10 = PseudoReadVLENB
+    ; CHECK: $x10 = SLLI killed $x10, 1
+    ; CHECK: $x2 = SUB $x2, killed $x10
+    ; CHECK: PseudoVSPILL_M1 $v0, $x2 :: (store unknown-size into %stack.1, align 8)
+    ; CHECK: $x10 = PseudoReadVLENB
+    ; CHECK: $x10 = ADD $x2, killed $x10
+    ; CHECK: PseudoVSPILL_M1 $v1, killed $x10 :: (store unknown-size into %stack.0, align 8)
+    ; CHECK: renamable $v0 = PseudoVRELOAD_M1 $x2 :: (load unknown-size from %stack.1, align 8)
+    ; CHECK: renamable $v25 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, $noreg, -1, implicit $vl, implicit $vtype
+    ; CHECK: $x10 = PseudoReadVLENB
+    ; CHECK: $x10 = ADD $x2, killed $x10
+    ; CHECK: renamable $v0 = PseudoVRELOAD_M1 killed $x10 :: (load unknown-size from %stack.0, align 8)
+    ; CHECK: renamable $v26 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, $noreg, -1, implicit $vl, implicit $vtype
+    ; CHECK: renamable $v0 = PseudoVADD_VV_M1 killed renamable $v25, killed renamable $v26, $noreg, -1, implicit $vl, implicit $vtype
+    ; CHECK: $x10 = PseudoReadVLENB
+    ; CHECK: $x10 = SLLI killed $x10, 1
+    ; CHECK: $x2 = ADD $x2, killed $x10
+    ; CHECK: PseudoRET implicit $v0
+    %0:vr = COPY $v0
+    %1:vr = COPY $v1
+    %2:vr = COPY $v2
+    %3:vr = COPY $v3
+    %4:vmv0 = COPY %0
+    %5:vrnov0 = PseudoVMERGE_VIM_M1 killed %2, 1, %4, $noreg, -1, implicit $vl, implicit $vtype
+    %6:vmv0 = COPY %1
+    %7:vrnov0 = PseudoVMERGE_VIM_M1 killed %3, 1, %6, $noreg, -1, implicit $vl, implicit $vtype
+    %8:vr = PseudoVADD_VV_M1 killed %5, killed %7, $noreg, -1, implicit $vl, implicit $vtype
+    $v0 = COPY %8
+    PseudoRET implicit $v0
+...