[PATCH] D97112: [X86][AMX] Lower tile copy instruction.

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


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Comment at: llvm/lib/Target/X86/X86RegisterInfo.cpp:878
     break;
+  case X86::COPY: {
+    Register SrcReg = MI->getOperand(1).getReg();
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pengfei wrote:
> Is it possible to define a special COPY for AMX which can implicitly define a register for stride?
Not sure. The COPY instruction is common for all target.


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Comment at: llvm/lib/Target/X86/X86TargetMachine.cpp:584
 
+void X86PassConfig::addPostCopy() { addPass(createX86LowerTileCopyPass()); }
+
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pengfei wrote:
> We are much like handling X87 register copy in pass "X86 FP Stackifier", so I think we can add the pass to addPostRegAlloc like it.
Sounds good to me.


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Comment at: llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll:37
+; CHECK-NEXT:    movabsq $64, %rax
+; CHECK-NEXT:    tilestored %tmm3, 2048(%rsp,%rax) # 1024-byte Folded Spill
+; CHECK-NEXT:    vzeroupper
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pengfei wrote:
> As we had discussed, tilezero should be rematerialized instead of spilling. For non tilezero cases, we still need to consider the spilling as loop invariant and hoist it out of the loop. Anyway, these are optimization thoughs which don't affect the functionality here.
I would do the optimization in another patch.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97112/new/

https://reviews.llvm.org/D97112