[llvm] 067ec53 - [AArch64][GlobalISel] Add selection support for G_VECREDUCE of <2 x i32>
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 20 00:53:43 PST 2021
Author: Amara Emerson
Date: 2021-02-20T00:39:38-08:00
New Revision: 067ec53df155e5bbe1c7a9c940f02bad6e36d9de
URL: https://github.com/llvm/llvm-project/commit/067ec53df155e5bbe1c7a9c940f02bad6e36d9de
DIFF: https://github.com/llvm/llvm-project/commit/067ec53df155e5bbe1c7a9c940f02bad6e36d9de.diff
LOG: [AArch64][GlobalISel] Add selection support for G_VECREDUCE of <2 x i32>
This selects to a pairwise add and a subreg copy.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index bf44fa73e53d..e34d18537b4d 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -3239,6 +3239,21 @@ bool AArch64InstructionSelector::selectReduction(
Register VecReg = I.getOperand(1).getReg();
LLT VecTy = MRI.getType(VecReg);
if (I.getOpcode() == TargetOpcode::G_VECREDUCE_ADD) {
+ // For <2 x i32> ADDPv2i32 generates an FPR64 value, so we need to emit
+ // a subregister copy afterwards.
+ if (VecTy == LLT::vector(2, 32)) {
+ MachineIRBuilder MIB(I);
+ Register DstReg = I.getOperand(0).getReg();
+ auto AddP = MIB.buildInstr(AArch64::ADDPv2i32, {&AArch64::FPR64RegClass},
+ {VecReg, VecReg});
+ auto Copy = MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {})
+ .addReg(AddP.getReg(0), 0, AArch64::ssub)
+ .getReg(0);
+ RBI.constrainGenericRegister(Copy, AArch64::FPR32RegClass, MRI);
+ I.eraseFromParent();
+ return constrainSelectedInstRegOperands(*AddP, TII, TRI, RBI);
+ }
+
unsigned Opc = 0;
if (VecTy == LLT::vector(16, 8))
Opc = AArch64::ADDVv16i8v;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
index 30d88932ec1b..afd5aa7dd9e3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
@@ -85,6 +85,33 @@ body: |
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
+...
+---
+name: add_S_v2i32
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+liveins:
+ - { reg: '$x0' }
+body: |
+ bb.1:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: add_S_v2i32
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8)
+ ; CHECK: [[ADDPv2i32_:%[0-9]+]]:fpr64 = ADDPv2i32 [[LDRDui]], [[LDRDui]]
+ ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[ADDPv2i32_]].ssub
+ ; CHECK: $w0 = COPY [[COPY1]]
+ ; CHECK: RET_ReallyLR implicit $w0
+ %0:gpr(p0) = COPY $x0
+ %1:fpr(<2 x s32>) = G_LOAD %0(p0) :: (load 8)
+ %2:fpr(s32) = G_VECREDUCE_ADD %1(<2 x s32>)
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+
...
---
name: add_D
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