[PATCH] D97054: [MachineVerifier] Confirm that both ends of a tied def/use are live together

[Serguei Katkov via Phabricator via llvm-commits]

skatkov added a comment.

In D97054#2574688 <https://reviews.llvm.org/D97054#2574688>, @reames wrote:

> Realized I'd only run the X86 tests.  Went and ran all targets, and hit some failures on AMDGPU and SystemZ.
>
> Failed Tests (8):
>
>   LLVM :: CodeGen/AMDGPU/GlobalISel/insertelement.ll
>   LLVM :: CodeGen/AMDGPU/indirect-addressing-si.ll
>   LLVM :: CodeGen/AMDGPU/insert_vector_dynelt.ll
>   LLVM :: CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
>   LLVM :: CodeGen/AMDGPU/r600.global_atomics.ll
>   LLVM :: CodeGen/SystemZ/asm-18.ll
>   LLVM :: CodeGen/SystemZ/fold-memory-op-impl.ll
>   LLVM :: CodeGen/SystemZ/int-cmp-44.ll

I took a look into another failure CodeGen/AMDGPU/r600.global_atomics.ll
After Register Coalescing added verification check complains about subrange.

  ********** MACHINEINSTRS **********
  # Machine code for function atomic_add_i32_offset: NoPHIs, TracksLiveness, TiedOpsRewritten
  
  0B	bb.0.entry:
  16B	  undef %4.sub0:r600_reg128 = MOV 1, 0, 0, 0, $alu_const, 0, 0, 0, 2058, 1, $pred_sel_off, 0, 0
  32B	  %1:r600_treg32_x = ADD_INT 0, 0, 1, 0, 0, 0, $alu_const, 0, 0, 0, 2057, $alu_literal_x, 0, 0, 0, -1, 1, $pred_sel_off, 16, 0
  80B	  dead %4:r600_reg128 = RAT_ATOMIC_ADD_NORET %4:r600_reg128(tied-def 0), %1:r600_treg32_x
  96B	  RETURN
  
  # End machine code for function atomic_add_i32_offset.
  
  *** Bad machine code: tied def w/o use in same live range ***
  - function:    atomic_add_i32_offset
  - basic block: %bb.0 entry (0x1bcdbd8) [0B;112B)
  - instruction: 80B	dead %4:r600_reg128 = RAT_ATOMIC_ADD_NORET %4:r600_reg128(tied-def 0), %1:r600_treg32_x
  - liverange:   [80r,80d:1)  0 at x 1 at 80r
  - v. register: %4
  - lanemask:    000000000000000E
  - ValNo:       1 (def 80r)

Here, 
16B	  undef %4.sub0:r600_reg128 = MOV 1, 0, 0, 0, $alu_const, 0, 0, 0, 2058, 1, $pred_sel_off, 0, 0
only subrange is defined.


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