[PATCH] D97112: [X86][AMX] Lower tile copy instruction.

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke created this revision.
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Since there is no tile copy instruction, we need to store tile
register to stack and load from stack to another tile register.
We need extra GR to hold the stride, and we need stack slot to
hold the tile data register. We would run this pass after copy
propagation, so that we don't miss copy optimization. And we
would run this pass before prolog/epilog insertion, so that we
can allocate stack slot.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97112

Files:
  llvm/include/llvm/CodeGen/TargetPassConfig.h
  llvm/lib/CodeGen/TargetPassConfig.cpp
  llvm/lib/Target/X86/CMakeLists.txt
  llvm/lib/Target/X86/X86.h
  llvm/lib/Target/X86/X86LowerTileCopy.cpp
  llvm/lib/Target/X86/X86RegisterInfo.cpp
  llvm/lib/Target/X86/X86TargetMachine.cpp
  llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll
  llvm/test/CodeGen/X86/opt-pipeline.ll

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