[PATCH] D97097: [RISCV] Custom isel the rest of the vector load/store intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 325142.
craig.topper added a comment.

Propagate memory operands if we happen to have them
clang-format


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97097/new/

https://reviews.llvm.org/D97097

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D97097.325142.patch
Type: text/x-patch
Size: 25774 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210220/feaaaef6/attachment.bin>