[llvm] 27566e9 - [AArch64][GlobalISel] Make G_VECREDUCE_ADD of <2 x s32> legal.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2021-02-19T14:28:21-08:00
New Revision: 27566e9c3e65f23da2634077d76c932b72b20281

URL: https://github.com/llvm/llvm-project/commit/27566e9c3e65f23da2634077d76c932b72b20281
DIFF: https://github.com/llvm/llvm-project/commit/27566e9c3e65f23da2634077d76c932b72b20281.diff

LOG: [AArch64][GlobalISel] Make G_VECREDUCE_ADD of <2 x s32> legal.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 09de46a6f18f..55c4028e7ce0 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -692,7 +692,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .lower();
 
   getActionDefinitionsBuilder(G_VECREDUCE_ADD)
-      .legalFor({{s8, v16s8}, {s16, v8s16}, {s32, v4s32}, {s64, v2s64}})
+      .legalFor(
+          {{s8, v16s8}, {s16, v8s16}, {s32, v4s32}, {s32, v2s32}, {s64, v2s64}})
       .lower();
 
   computeTables();

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
index 78e36356e315..2d83db4f9602 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
@@ -88,3 +88,24 @@ body:             |
     RET_ReallyLR implicit $x0
 
 ...
+---
+name:            add_v2s32
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: add_v2s32
+    ; CHECK: liveins: $x0
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load 8)
+    ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<2 x s32>)
+    ; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %0:_(p0) = COPY $x0
+    %1:_(<2 x s32>) = G_LOAD %0(p0) :: (load 8)
+    %2:_(s32) = G_VECREDUCE_ADD %1(<2 x s32>)
+    $w0 = COPY %2(s32)
+    RET_ReallyLR implicit $w0
+
+...