[llvm] e7c86f4 - [RISCV] Use inheritance to reduce some repeated code in tablegen. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-02-19T10:42:18-08:00
New Revision: e7c86f4ac4f24db10b607bc0f38586e0d3af2ec4

URL: https://github.com/llvm/llvm-project/commit/e7c86f4ac4f24db10b607bc0f38586e0d3af2ec4
DIFF: https://github.com/llvm/llvm-project/commit/e7c86f4ac4f24db10b607bc0f38586e0d3af2ec4.diff

LOG: [RISCV] Use inheritance to reduce some repeated code in tablegen. NFC

The VLX and VSX searchable tables, share the same format so we
can have a common base class for them.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index df4b2197a57b..5d7026621121 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -413,7 +413,7 @@ def RISCVVIntrinsicsTable : GenericTable {
   let PrimaryKeyName = "getRISCVVIntrinsicInfo";
 }
 
-class RISCVVLX<bit M, bit O, bits<7> S, bits<3> L, bits<3> IL> {
+class RISCVVLX_VSX<bit M, bit O, bits<7> S, bits<3> L, bits<3> IL> {
   bits<1> Masked = M;
   bits<1> Ordered = O;
   bits<7> SEW = S;
@@ -422,28 +422,24 @@ class RISCVVLX<bit M, bit O, bits<7> S, bits<3> L, bits<3> IL> {
   Pseudo Pseudo = !cast<Pseudo>(NAME);
 }
 
-def RISCVVLXTable : GenericTable {
-  let FilterClass = "RISCVVLX";
+class RISCVVLX<bit M, bit O, bits<7> S, bits<3> L, bits<3> IL> :
+  RISCVVLX_VSX<M, O, S, L, IL>;
+class RISCVVSX<bit M, bit O, bits<7> S, bits<3> L, bits<3> IL> :
+  RISCVVLX_VSX<M, O, S, L, IL>;
+
+class RISCVVLX_VSXTable : GenericTable {
   let CppTypeName = "VLX_VSXPseudo";
   let Fields = ["Masked", "Ordered", "SEW", "LMUL", "IndexLMUL", "Pseudo"];
   let PrimaryKey = ["Masked", "Ordered", "SEW", "LMUL", "IndexLMUL"];
-  let PrimaryKeyName = "getVLXPseudo";
 }
 
-class RISCVVSX<bit M, bit O, bits<7> S, bits<3> L, bits<3> IL> {
-  bits<1> Masked = M;
-  bits<1> Ordered = O;
-  bits<7> SEW = S;
-  bits<3> LMUL = L;
-  bits<3> IndexLMUL = IL;
-  Pseudo Pseudo = !cast<Pseudo>(NAME);
+def RISCVVLXTable : RISCVVLX_VSXTable {
+  let FilterClass = "RISCVVLX";
+  let PrimaryKeyName = "getVLXPseudo";
 }
 
-def RISCVVSXTable : GenericTable {
+def RISCVVSXTable : RISCVVLX_VSXTable {
   let FilterClass = "RISCVVSX";
-  let CppTypeName = "VLX_VSXPseudo";
-  let Fields = ["Masked", "Ordered", "SEW", "LMUL", "IndexLMUL", "Pseudo"];
-  let PrimaryKey = ["Masked", "Ordered", "SEW", "LMUL", "IndexLMUL"];
   let PrimaryKeyName = "getVSXPseudo";
 }