[llvm] dbf910f - [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 19 10:07:22 PST 2021
Author: Craig Topper
Date: 2021-02-19T10:07:12-08:00
New Revision: dbf910f0d95011e9485af859a10efb75bf28ee89
URL: https://github.com/llvm/llvm-project/commit/dbf910f0d95011e9485af859a10efb75bf28ee89
DIFF: https://github.com/llvm/llvm-project/commit/dbf910f0d95011e9485af859a10efb75bf28ee89.diff
LOG: [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.
Just like we do for isel patterns, we need to call selectVLOp
to prevent 0 from being selected to X0 by the default isel.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D97021
Added:
llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 95a3144d4455..0cd9b6cec768 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -201,7 +201,9 @@ void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, bool IsMasked,
Operands.push_back(Node->getOperand(CurOp++)); // Stride.
if (IsMasked)
Operands.push_back(Node->getOperand(CurOp++)); // Mask.
- Operands.push_back(Node->getOperand(CurOp++)); // VL.
+ SDValue VL;
+ selectVLOp(Node->getOperand(CurOp++), VL);
+ Operands.push_back(VL);
Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain.
const RISCV::VLSEGPseudo *P =
@@ -240,7 +242,9 @@ void RISCVDAGToDAGISel::selectVLSEGFF(SDNode *Node, bool IsMasked) {
Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
if (IsMasked)
Operands.push_back(Node->getOperand(CurOp++)); // Mask.
- Operands.push_back(Node->getOperand(CurOp++)); // VL.
+ SDValue VL;
+ selectVLOp(Node->getOperand(CurOp++), VL);
+ Operands.push_back(VL);
Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain.
const RISCV::VLSEGPseudo *P =
@@ -285,7 +289,9 @@ void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, bool IsMasked,
MVT IndexVT = Operands.back()->getSimpleValueType(0);
if (IsMasked)
Operands.push_back(Node->getOperand(CurOp++)); // Mask.
- Operands.push_back(Node->getOperand(CurOp++)); // VL.
+ SDValue VL;
+ selectVLOp(Node->getOperand(CurOp++), VL);
+ Operands.push_back(VL);
Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain.
@@ -329,7 +335,9 @@ void RISCVDAGToDAGISel::selectVSSEG(SDNode *Node, bool IsMasked,
Operands.push_back(Node->getOperand(CurOp++)); // Stride.
if (IsMasked)
Operands.push_back(Node->getOperand(CurOp++)); // Mask.
- Operands.push_back(Node->getOperand(CurOp++)); // VL.
+ SDValue VL;
+ selectVLOp(Node->getOperand(CurOp++), VL);
+ Operands.push_back(VL);
Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain.
const RISCV::VSSEGPseudo *P = RISCV::getVSSEGPseudo(
@@ -360,7 +368,9 @@ void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, bool IsMasked,
MVT IndexVT = Operands.back()->getSimpleValueType(0);
if (IsMasked)
Operands.push_back(Node->getOperand(CurOp++)); // Mask.
- Operands.push_back(Node->getOperand(CurOp++)); // VL.
+ SDValue VL;
+ selectVLOp(Node->getOperand(CurOp++), VL);
+ Operands.push_back(VL);
Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain.
diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
new file mode 100644
index 000000000000..925454b391e7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
@@ -0,0 +1,261 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+
+; Make sure we don't select a 0 vl to X0 in the custom isel handlers we use
+; for these intrinsics.
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(i16* , i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlseg2_mask_nxv16i16(i16* %base, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlseg2_mask_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mv a1, zero
+; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT: vlseg2e16.v v4, (a0)
+; CHECK-NEXT: vmv4r.v v8, v4
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i64 0)
+ %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+ %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i1> %mask, i64 0)
+ %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+ ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(i16*, i64, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(i16* %base, i64 %offset, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mv a2, zero
+; CHECK-NEXT: vsetvli a3, a2, e16,m4,ta,mu
+; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
+; CHECK-NEXT: vmv4r.v v8, v4
+; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu
+; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i64 %offset, i64 0)
+ %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+ %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0)
+ %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+ ret <vscale x 16 x i16> %3
+}
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vloxseg2_mask_nxv16i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vloxseg2_mask_nxv16i16_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mv a1, zero
+; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT: vloxseg2ei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v16, v12
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT: vloxseg2ei16.v v12, (a0), v8, v0.t
+; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 0)
+ %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+ %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
+ %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+ ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mv a1, zero
+; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
+; CHECK-NEXT: vluxseg2ei16.v v12, (a0), v8
+; CHECK-NEXT: vmv4r.v v16, v12
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
+; CHECK-NEXT: vluxseg2ei16.v v12, (a0), v8, v0.t
+; CHECK-NEXT: vmv4r.v v8, v16
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 0)
+ %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
+ %2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
+ %3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
+ ret <vscale x 16 x i16> %3
+}
+
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64)
+declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
+
+define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i64* %outvl) {
+; CHECK-LABEL: test_vlseg2ff_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mv a2, zero
+; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
+; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
+; CHECK-NEXT: csrr a0, vl
+; CHECK-NEXT: sd a0, 0(a1)
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 0)
+ %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
+ %2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
+ store i64 %2, i64* %outvl
+ ret <vscale x 16 x i16> %1
+}
+
+define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64* %outvl) {
+; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmv4r.v v4, v8
+; CHECK-NEXT: mv a2, zero
+; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu
+; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
+; CHECK-NEXT: csrr a0, vl
+; CHECK-NEXT: sd a0, 0(a1)
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 0)
+ %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
+ %2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
+ store i64 %2, i64* %outvl
+ ret <vscale x 16 x i16> %1
+}
+
+declare void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)
+declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
+
+define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base) {
+; CHECK-LABEL: test_vsseg2_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT: vmv4r.v v12, v8
+; CHECK-NEXT: mv a1, zero
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v8, (a0)
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 0)
+ ret void
+}
+
+define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vsseg2_mask_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT: vmv4r.v v12, v8
+; CHECK-NEXT: mv a1, zero
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 0)
+ ret void
+}
+
+declare void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, i64)
+declare void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64)
+
+define void @test_vssseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset) {
+; CHECK-LABEL: test_vssseg2_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT: vmv4r.v v12, v8
+; CHECK-NEXT: mv a2, zero
+; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
+; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, i64 0)
+ ret void
+}
+
+define void @test_vssseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vssseg2_mask_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT: vmv4r.v v12, v8
+; CHECK-NEXT: mv a2, zero
+; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
+; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0)
+ ret void
+}
+
+declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsoxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index) {
+; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v12, v8
+; CHECK-NEXT: mv a1, zero
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)
+ ret void
+}
+
+define void @test_vsoxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v12, v8
+; CHECK-NEXT: mv a1, zero
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
+ ret void
+}
+
+declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsuxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index) {
+; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v12, v8
+; CHECK-NEXT: mv a1, zero
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)
+ ret void
+}
+
+define void @test_vsuxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT: vmv4r.v v28, v12
+; CHECK-NEXT: vmv4r.v v12, v8
+; CHECK-NEXT: mv a1, zero
+; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
+; CHECK-NEXT: ret
+entry:
+ tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
+ ret void
+}
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