[llvm] 8d3442e - [AArch64][GlobalISel] Run redundant_sext_inreg in the post-legalizer combiner
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 19 09:36:26 PST 2021
Author: Jessica Paquette
Date: 2021-02-19T09:34:47-08:00
New Revision: 8d3442eddb88e2e52bee89f333df0c6cf12e1237
URL: https://github.com/llvm/llvm-project/commit/8d3442eddb88e2e52bee89f333df0c6cf12e1237
DIFF: https://github.com/llvm/llvm-project/commit/8d3442eddb88e2e52bee89f333df0c6cf12e1237.diff
LOG: [AArch64][GlobalISel] Run redundant_sext_inreg in the post-legalizer combiner
This is to ensure that we can eliminate G_ASSERT_SEXT.
In a follow-up patch, I'm going to make CallLowering emit G_ASSERT_SEXT for
signext parameters.
Differential Revision: https://reviews.llvm.org/D96913
Added:
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir
Modified:
llvm/lib/Target/AArch64/AArch64Combine.td
llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 980d61dde1d7..59988af493c2 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -145,6 +145,6 @@ def AArch64PostLegalizerCombinerHelper
hoist_logic_op_with_same_opcode_hands,
redundant_and, xor_of_and_with_same_reg,
extractvecelt_pairwise_add, redundant_or,
- mul_const]> {
+ mul_const, redundant_sext_inreg]> {
let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir
index 43f061800ca1..523a1cc7ce85 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-trunc-sextload.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
---
name: test_combine_sext_trunc_of_sextload
legalized: true
@@ -49,8 +50,7 @@ body: |
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 24
- ; CHECK: $w0 = COPY [[SEXT_INREG]](s32)
+ ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_SEXTLOAD %0:_(p0) :: (load 2)
%2:_(s32) = COPY %1:_(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir
new file mode 100644
index 000000000000..11c6cedf8344
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir
@@ -0,0 +1,83 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name: sextload
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: sextload
+ ; CHECK: liveins: $x0
+ ; CHECK: %x0:_(p0) = COPY $x0
+ ; CHECK: %sextload:_(s32) = G_SEXTLOAD %x0(p0) :: (load 2)
+ ; CHECK: $w0 = COPY %sextload(s32)
+ %x0:_(p0) = COPY $x0
+ %sextload:_(s32) = G_SEXTLOAD %x0:_(p0) :: (load 2)
+ %sext_inreg:_(s32) = G_SEXT_INREG %sextload:_(s32), 24
+ $w0 = COPY %sext_inreg(s32)
+...
+---
+name: assert_sext
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $w0
+ ; The G_ASSERT_SEXT says we already sign extended from 24 bits, so the
+ ; G_SEXT_INREG is not necessary.
+
+ ; CHECK-LABEL: name: assert_sext
+ ; CHECK: liveins: $w0
+ ; CHECK: %w0:_(s32) = COPY $w0
+ ; CHECK: %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
+ ; CHECK: $w0 = COPY %assert_sext(s32)
+ %w0:_(s32) = COPY $w0
+ %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
+ %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext:_(s32), 24
+ $w0 = COPY %sext_inreg(s32)
+...
+---
+name: assert_sext_greater_width
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $w0
+ ; The G_ASSERT_SEXT is from a wider width than the G_SEXT_INREG, so we
+ ; can't eliminate it.
+
+ ; CHECK-LABEL: name: assert_sext_greater_width
+ ; CHECK: liveins: $w0
+ ; CHECK: %w0:_(s32) = COPY $w0
+ ; CHECK: %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
+ ; CHECK: %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext, 12
+ ; CHECK: $w0 = COPY %sext_inreg(s32)
+ %w0:_(s32) = COPY $w0
+ %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
+ %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext:_(s32), 12
+ $w0 = COPY %sext_inreg(s32)
+...
+---
+name: assert_sext_smaller_width
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $w0
+ ; The G_ASSERT_SEXT is from a smaller width, so the G_SEXT_INREG is not
+ ; necessary.
+
+ ; CHECK-LABEL: name: assert_sext_smaller_width
+ ; CHECK: liveins: $w0
+ ; CHECK: %w0:_(s32) = COPY $w0
+ ; CHECK: %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 8
+ ; CHECK: $w0 = COPY %assert_sext(s32)
+ %w0:_(s32) = COPY $w0
+ %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 8
+ %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext:_(s32), 12
+ $w0 = COPY %sext_inreg(s32)
+...
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