[PATCH] D97062: [AMDGPU] Use divergent addresses for vector loads

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

> This shows up some problems in the idot tests where we fail to select
> v_dot instructions because the patterns only match MUL_[UI]24 ISD nodes,
> but the DAG contains i16 mul nodes instead.

Is selecting these from patterns actually an important use case? Or does everyone use the intrinsics instead?


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  https://reviews.llvm.org/D97062/new/

https://reviews.llvm.org/D97062