[llvm] b2c7f06 - [AMDGPU] Add some GFX9 test coverage. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 19 06:39:54 PST 2021
Author: Jay Foad
Date: 2021-02-19T14:38:52Z
New Revision: b2c7f06db1d0892a22c4c159383ca40c533d9244
URL: https://github.com/llvm/llvm-project/commit/b2c7f06db1d0892a22c4c159383ca40c533d9244
DIFF: https://github.com/llvm/llvm-project/commit/b2c7f06db1d0892a22c4c159383ca40c533d9244.diff
LOG: [AMDGPU] Add some GFX9 test coverage. NFC.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index 7eec033fa271..5e28babc70b4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare -amdgpu-bypass-slow-div=0 %s | FileCheck %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GFX9 %s
define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
; CHECK-LABEL: @udiv_i32(
@@ -37,35 +38,63 @@ define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
; CHECK-NEXT: store i32 [[TMP29]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GCN-NEXT: s_sub_i32 s4, 0, s3
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_lo_u32 v1, s4, v0
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s2, v0
-; GCN-NEXT: v_mul_lo_u32 v1, v0, s3
-; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3
+; GFX6-NEXT: s_sub_i32 s4, 0, s3
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
+; GFX9-NEXT: s_sub_i32 s4, 0, s3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = udiv i32 %x, %y
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -103,32 +132,59 @@ define amdgpu_kernel void @urem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
; CHECK-NEXT: store i32 [[TMP27]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5
-; GCN-NEXT: s_sub_i32 s2, 0, s5
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_lo_u32 v1, s2, v0
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s4, v0
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s5
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s5, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s5, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s5, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s5, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s5
+; GFX6-NEXT: s_sub_i32 s2, 0, s5
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, s2, v0
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s5
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s5, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s5, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s5, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s5, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
+; GFX9-NEXT: s_sub_i32 s4, 0, s3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = urem i32 %x, %y
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -177,43 +233,80 @@ define amdgpu_kernel void @sdiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
; CHECK-NEXT: store i32 [[TMP38]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s8, s3, 31
-; GCN-NEXT: s_add_i32 s3, s3, s8
-; GCN-NEXT: s_xor_b32 s9, s3, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9
-; GCN-NEXT: s_sub_i32 s3, 0, s9
-; GCN-NEXT: s_ashr_i32 s0, s2, 31
-; GCN-NEXT: s_add_i32 s1, s2, s0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: s_xor_b32 s1, s1, s0
-; GCN-NEXT: s_xor_b32 s2, s0, s8
-; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_lo_u32 v1, s3, v0
-; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
-; GCN-NEXT: v_mul_lo_u32 v1, v0, s9
-; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v1
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s9, v1
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: v_xor_b32_e32 v0, s2, v0
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s8, s3, 31
+; GFX6-NEXT: s_add_i32 s3, s3, s8
+; GFX6-NEXT: s_xor_b32 s9, s3, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s9
+; GFX6-NEXT: s_sub_i32 s3, 0, s9
+; GFX6-NEXT: s_ashr_i32 s0, s2, 31
+; GFX6-NEXT: s_add_i32 s1, s2, s0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: s_xor_b32 s1, s1, s0
+; GFX6-NEXT: s_xor_b32 s2, s0, s8
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, v0, s9
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s9, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s4, s3, 31
+; GFX9-NEXT: s_add_i32 s3, s3, s4
+; GFX9-NEXT: s_xor_b32 s5, s3, s4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s5
+; GFX9-NEXT: s_sub_i32 s3, 0, s5
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX9-NEXT: s_ashr_i32 s3, s2, 31
+; GFX9-NEXT: s_add_i32 s2, s2, s3
+; GFX9-NEXT: s_xor_b32 s2, s2, s3
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: s_xor_b32 s3, s3, s4
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v0, s5
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s3, v0
+; GFX9-NEXT: v_subrev_u32_e32 v0, s3, v0
+; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = sdiv i32 %x, %y
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -259,40 +352,75 @@ define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
; CHECK-NEXT: store i32 [[TMP35]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s4, s3, 31
-; GCN-NEXT: s_add_i32 s3, s3, s4
-; GCN-NEXT: s_xor_b32 s6, s3, s4
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GCN-NEXT: s_sub_i32 s3, 0, s6
-; GCN-NEXT: s_ashr_i32 s4, s2, 31
-; GCN-NEXT: s_add_i32 s2, s2, s4
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: s_xor_b32 s5, s2, s4
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_lo_u32 v1, s3, v0
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s5, v0
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s6
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
-; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-NEXT: v_xor_b32_e32 v0, s4, v0
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s4, s3, 31
+; GFX6-NEXT: s_add_i32 s3, s3, s4
+; GFX6-NEXT: s_xor_b32 s6, s3, s4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GFX6-NEXT: s_sub_i32 s3, 0, s6
+; GFX6-NEXT: s_ashr_i32 s4, s2, 31
+; GFX6-NEXT: s_add_i32 s2, s2, s4
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: s_xor_b32 s5, s2, s4
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s4, s3, 31
+; GFX9-NEXT: s_add_i32 s3, s3, s4
+; GFX9-NEXT: s_xor_b32 s3, s3, s4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
+; GFX9-NEXT: s_sub_i32 s4, 0, s3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX9-NEXT: s_ashr_i32 s4, s2, 31
+; GFX9-NEXT: s_add_i32 s2, s2, s4
+; GFX9-NEXT: s_xor_b32 s2, s2, s4
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_subrev_u32_e32 v0, s4, v0
+; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = srem i32 %x, %y
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -320,26 +448,46 @@ define amdgpu_kernel void @udiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
; CHECK-NEXT: store i16 [[TMP17]], i16 addrspace(1)* [[OUT:%.*]], align 2
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dword s2, s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b32 s3, s2, 16
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GCN-NEXT: s_and_b32 s2, s2, 0xffff
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dword s2, s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshr_b32 s3, s2, 16
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3
+; GFX6-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s2
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshr_b32 s3, s2, 16
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
+; GFX9-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v2
+; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
+; GFX9-NEXT: global_store_short v3, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = udiv i16 %x, %y
store i16 %r, i16 addrspace(1)* %out
ret void
@@ -369,28 +517,51 @@ define amdgpu_kernel void @urem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
; CHECK-NEXT: store i16 [[TMP19]], i16 addrspace(1)* [[OUT:%.*]], align 2
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b32 s2, s4, 16
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GCN-NEXT: s_and_b32 s3, s4, 0xffff
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dword s4, s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshr_b32 s2, s4, 16
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GFX6-NEXT: s_and_b32 s3, s4, 0xffff
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshr_b32 s3, s2, 16
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
+; GFX9-NEXT: s_and_b32 s4, s2, 0xffff
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s4
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
+; GFX9-NEXT: global_store_short v1, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = urem i16 %x, %y
store i16 %r, i16 addrspace(1)* %out
ret void
@@ -422,31 +593,56 @@ define amdgpu_kernel void @sdiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
; CHECK-NEXT: store i16 [[TMP21]], i16 addrspace(1)* [[OUT:%.*]], align 2
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s1, s0, 16
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1
-; GCN-NEXT: s_sext_i32_i16 s0, s0
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0
-; GCN-NEXT: s_xor_b32 s0, s0, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mov_b32_e32 v3, s0
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s1, s0, 16
+; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s1
+; GFX6-NEXT: s_sext_i32_i16 s0, s0
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s0
+; GFX6-NEXT: s_xor_b32 s0, s0, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mov_b32_e32 v3, s0
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: buffer_store_short v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s0, s4, 16
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s0
+; GFX9-NEXT: s_sext_i32_i16 s1, s4
+; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s1
+; GFX9-NEXT: s_xor_b32 s0, s1, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s4, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s4, 0
+; GFX9-NEXT: v_add_u32_e32 v0, s0, v3
+; GFX9-NEXT: global_store_short v1, v0, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = sdiv i16 %x, %y
store i16 %r, i16 addrspace(1)* %out
ret void
@@ -480,33 +676,61 @@ define amdgpu_kernel void @srem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
; CHECK-NEXT: store i16 [[TMP23]], i16 addrspace(1)* [[OUT:%.*]], align 2
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s2, s4, 16
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2
-; GCN-NEXT: s_sext_i32_i16 s3, s4
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3
-; GCN-NEXT: s_xor_b32 s3, s3, s2
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_ashr_i32 s3, s3, 30
-; GCN-NEXT: s_or_b32 s3, s3, 1
-; GCN-NEXT: v_mov_b32_e32 v3, s3
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dword s4, s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s2, s4, 16
+; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s2
+; GFX6-NEXT: s_sext_i32_i16 s3, s4
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s3
+; GFX6-NEXT: s_xor_b32 s3, s3, s2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_ashr_i32 s3, s3, 30
+; GFX6-NEXT: s_or_b32 s3, s3, 1
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s5, s4, 16
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s5
+; GFX9-NEXT: s_sext_i32_i16 s2, s4
+; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s2
+; GFX9-NEXT: s_xor_b32 s2, s2, s5
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX9-NEXT: s_ashr_i32 s2, s2, 30
+; GFX9-NEXT: s_or_b32 s6, s2, 1
+; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, v2
+; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX9-NEXT: s_cselect_b32 s2, s6, 0
+; GFX9-NEXT: v_add_u32_e32 v0, s2, v2
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
+; GFX9-NEXT: global_store_short v1, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = srem i16 %x, %y
store i16 %r, i16 addrspace(1)* %out
ret void
@@ -534,24 +758,42 @@ define amdgpu_kernel void @udiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
; CHECK-NEXT: store i8 [[TMP17]], i8 addrspace(1)* [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_i8:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_cvt_f32_ubyte1_e32 v0, s0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, s0
-; GCN-NEXT: v_mul_f32_e32 v1, v2, v1
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v1
-; GCN-NEXT: v_mad_f32 v1, -v1, v0, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_i8:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_ubyte1_e32 v0, s0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s0
+; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v1
+; GFX6-NEXT: v_mad_f32 v1, -v1, v0, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte1_e32 v0, s2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, s2
+; GFX9-NEXT: v_mul_f32_e32 v1, v3, v1
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v1
+; GFX9-NEXT: v_mad_f32 v1, -v1, v0, v3
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
+; GFX9-NEXT: global_store_byte v2, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = udiv i8 %x, %y
store i8 %r, i8 addrspace(1)* %out
ret void
@@ -581,27 +823,49 @@ define amdgpu_kernel void @urem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
; CHECK-NEXT: store i8 [[TMP19]], i8 addrspace(1)* [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_i8:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_cvt_f32_ubyte1_e32 v0, s4
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, s4
-; GCN-NEXT: s_lshr_b32 s2, s4, 8
-; GCN-NEXT: v_mul_f32_e32 v1, v2, v1
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v1
-; GCN-NEXT: v_mad_f32 v1, -v1, v0, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GCN-NEXT: buffer_store_byte v0, off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_i8:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dword s4, s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_ubyte1_e32 v0, s4
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s4
+; GFX6-NEXT: s_lshr_b32 s2, s4, 8
+; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v1
+; GFX6-NEXT: v_mad_f32 v1, -v1, v0, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_ubyte1_e32 v0, s2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, s2
+; GFX9-NEXT: s_lshr_b32 s3, s2, 8
+; GFX9-NEXT: v_mul_f32_e32 v1, v2, v1
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v1
+; GFX9-NEXT: v_mad_f32 v1, -v1, v0, v2
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
+; GFX9-NEXT: global_store_byte v1, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = urem i8 %x, %y
store i8 %r, i8 addrspace(1)* %out
ret void
@@ -633,31 +897,56 @@ define amdgpu_kernel void @sdiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
; CHECK-NEXT: store i8 [[TMP21]], i8 addrspace(1)* [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_i8:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_bfe_i32 s1, s0, 0x80008
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1
-; GCN-NEXT: s_sext_i32_i8 s0, s0
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0
-; GCN-NEXT: s_xor_b32 s0, s0, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mov_b32_e32 v3, s0
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_i8:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_i32 s1, s0, 0x80008
+; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s1
+; GFX6-NEXT: s_sext_i32_i8 s0, s0
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s0
+; GFX6-NEXT: s_xor_b32 s0, s0, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mov_b32_e32 v3, s0
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_bfe_i32 s0, s4, 0x80008
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s0
+; GFX9-NEXT: s_sext_i32_i8 s1, s4
+; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s1
+; GFX9-NEXT: s_xor_b32 s0, s1, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s4, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s4, 0
+; GFX9-NEXT: v_add_u32_e32 v0, s0, v3
+; GFX9-NEXT: global_store_byte v1, v0, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = sdiv i8 %x, %y
store i8 %r, i8 addrspace(1)* %out
ret void
@@ -691,34 +980,63 @@ define amdgpu_kernel void @srem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
; CHECK-NEXT: store i8 [[TMP23]], i8 addrspace(1)* [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_i8:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_bfe_i32 s1, s0, 0x80008
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1
-; GCN-NEXT: s_sext_i32_i8 s3, s0
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3
-; GCN-NEXT: s_xor_b32 s1, s3, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_ashr_i32 s1, s1, 30
-; GCN-NEXT: s_or_b32 s1, s1, 1
-; GCN-NEXT: v_mov_b32_e32 v3, s1
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GCN-NEXT: s_lshr_b32 s2, s0, 8
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_i8:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_i32 s1, s0, 0x80008
+; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s1
+; GFX6-NEXT: s_sext_i32_i8 s3, s0
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s3
+; GFX6-NEXT: s_xor_b32 s1, s3, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_ashr_i32 s1, s1, 30
+; GFX6-NEXT: s_or_b32 s1, s1, 1
+; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: s_lshr_b32 s2, s0, 8
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_bfe_i32 s2, s4, 0x80008
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s2
+; GFX9-NEXT: s_sext_i32_i8 s3, s4
+; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s3
+; GFX9-NEXT: s_xor_b32 s2, s3, s2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX9-NEXT: s_ashr_i32 s2, s2, 30
+; GFX9-NEXT: s_lshr_b32 s5, s4, 8
+; GFX9-NEXT: s_or_b32 s6, s2, 1
+; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, v2
+; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX9-NEXT: s_cselect_b32 s2, s6, 0
+; GFX9-NEXT: v_add_u32_e32 v0, s2, v2
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
+; GFX9-NEXT: global_store_byte v1, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = srem i8 %x, %y
store i8 %r, i8 addrspace(1)* %out
ret void
@@ -857,92 +1175,178 @@ define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x
; CHECK-NEXT: store <4 x i32> [[TMP128]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_v4i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s3, 0x4f7ffffe
-; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s15, 0xf000
-; GCN-NEXT: s_mov_b32 s14, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9
-; GCN-NEXT: s_sub_i32 s2, 0, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v4, s10
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GCN-NEXT: v_cvt_f32_u32_e32 v6, s11
-; GCN-NEXT: v_mul_f32_e32 v0, s3, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s3, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mul_lo_u32 v2, s2, v0
-; GCN-NEXT: s_sub_i32 s2, 0, s9
-; GCN-NEXT: v_mul_lo_u32 v3, s2, v1
-; GCN-NEXT: s_sub_i32 s2, 0, s10
-; GCN-NEXT: v_mul_hi_u32 v2, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s4, v0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; GCN-NEXT: v_mul_hi_u32 v1, s5, v1
-; GCN-NEXT: v_mul_lo_u32 v2, v0, s8
-; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v0
-; GCN-NEXT: v_mul_lo_u32 v5, v1, s9
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s4, v2
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s8, v2
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v4
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s5, v5
-; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v1
-; GCN-NEXT: v_mul_f32_e32 v2, s3, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v3
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s9, v3
-; GCN-NEXT: v_mul_lo_u32 v4, s2, v2
-; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v1
-; GCN-NEXT: s_sub_i32 s0, 0, s11
-; GCN-NEXT: v_mul_hi_u32 v4, v2, v4
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v6
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GCN-NEXT: v_mul_hi_u32 v2, s6, v2
-; GCN-NEXT: v_mul_f32_e32 v4, s3, v4
-; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GCN-NEXT: v_mul_lo_u32 v3, v2, s10
-; GCN-NEXT: v_add_i32_e32 v6, vcc, 1, v2
-; GCN-NEXT: v_mul_lo_u32 v5, s0, v4
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s6, v3
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v3
-; GCN-NEXT: v_mul_hi_u32 v5, v4, v5
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v6, vcc, s10, v3
-; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_mul_hi_u32 v4, s7, v4
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v2
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
-; GCN-NEXT: v_mul_lo_u32 v6, v4, s11
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v4
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s7, v6
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v3
-; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s11, v3
-; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v4
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
-; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_v4i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s3, 0x4f7ffffe
+; GFX6-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s15, 0xf000
+; GFX6-NEXT: s_mov_b32 s14, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
+; GFX6-NEXT: s_sub_i32 s2, 0, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s10
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s11
+; GFX6-NEXT: v_mul_f32_e32 v0, s3, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, s3, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
+; GFX6-NEXT: s_sub_i32 s2, 0, s9
+; GFX6-NEXT: v_mul_lo_u32 v3, s2, v1
+; GFX6-NEXT: s_sub_i32 s2, 0, s10
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
+; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s8
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
+; GFX6-NEXT: v_mul_lo_u32 v5, v1, s9
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s4, v2
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s5, v5
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1
+; GFX6-NEXT: v_mul_f32_e32 v2, s3, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s9, v3
+; GFX6-NEXT: v_mul_lo_u32 v4, s2, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v1
+; GFX6-NEXT: s_sub_i32 s0, 0, s11
+; GFX6-NEXT: v_mul_hi_u32 v4, v2, v4
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v6
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT: v_mul_hi_u32 v2, s6, v2
+; GFX6-NEXT: v_mul_f32_e32 v4, s3, v4
+; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX6-NEXT: v_mul_lo_u32 v3, v2, s10
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v2
+; GFX6-NEXT: v_mul_lo_u32 v5, s0, v4
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s6, v3
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v3
+; GFX6-NEXT: v_mul_hi_u32 v5, v4, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s10, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT: v_mul_hi_u32 v4, s7, v4
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v6, v4, s11
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s7, v6
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s11, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_v4i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
+; GFX9-NEXT: s_mov_b32 s12, 0x4f7ffffe
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
+; GFX9-NEXT: s_sub_i32 s2, 0, s8
+; GFX9-NEXT: s_sub_i32 s3, 0, s9
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s10
+; GFX9-NEXT: v_mul_f32_e32 v0, s12, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, s12, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
+; GFX9-NEXT: s_sub_i32 s2, 0, s10
+; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_f32_e32 v2, s12, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, s8
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, s8, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s11
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, s2, v2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, s9
+; GFX9-NEXT: s_sub_i32 s2, 0, s11
+; GFX9-NEXT: v_mul_hi_u32 v6, v2, v6
+; GFX9-NEXT: v_mul_f32_e32 v3, s12, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v6
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v1
+; GFX9-NEXT: v_mul_lo_u32 v6, s2, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v7, s9, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-NEXT: v_mul_hi_u32 v2, s6, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5
+; GFX9-NEXT: v_mul_hi_u32 v5, v3, v6
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v1
+; GFX9-NEXT: v_mul_lo_u32 v8, v2, s10
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, s7, v3
+; GFX9-NEXT: v_sub_u32_e32 v6, s6, v8
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v6
+; GFX9-NEXT: v_subrev_u32_e32 v5, s10, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, v3, s11
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v5
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v2
+; GFX9-NEXT: v_sub_u32_e32 v5, s7, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, s11, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-NEXT: s_endpgm
%r = udiv <4 x i32> %x, %y
store <4 x i32> %r, <4 x i32> addrspace(1)* %out
ret void
@@ -1073,84 +1477,162 @@ define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x
; CHECK-NEXT: store <4 x i32> [[TMP120]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_v4i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s13, 0x4f7ffffe
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9
-; GCN-NEXT: s_sub_i32 s2, 0, s8
-; GCN-NEXT: s_sub_i32 s12, 0, s9
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s10
-; GCN-NEXT: v_cvt_f32_u32_e32 v5, s11
-; GCN-NEXT: v_mul_f32_e32 v0, s13, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s13, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GCN-NEXT: v_mul_lo_u32 v2, s2, v0
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_mul_lo_u32 v4, s12, v1
-; GCN-NEXT: v_mul_hi_u32 v2, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s4, v0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v4, v1
-; GCN-NEXT: v_mul_hi_u32 v1, s5, v1
-; GCN-NEXT: v_mul_f32_e32 v2, s13, v3
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s8
-; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s9
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s8, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s8, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
-; GCN-NEXT: s_sub_i32 s4, 0, s10
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GCN-NEXT: v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s9, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GCN-NEXT: v_mul_hi_u32 v3, v2, v3
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v5
-; GCN-NEXT: s_sub_i32 s4, 0, s11
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mul_f32_e32 v3, s13, v4
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s9, v1
-; GCN-NEXT: v_mul_hi_u32 v2, s6, v2
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
-; GCN-NEXT: v_mul_lo_u32 v5, s4, v3
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v2, s10
-; GCN-NEXT: v_mul_hi_u32 v4, v3, v5
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
-; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s10, v2
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT: v_mul_hi_u32 v3, s7, v3
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s10, v2
-; GCN-NEXT: v_mul_lo_u32 v3, v3, s11
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s7, v3
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s11, v3
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s11, v3
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_v4i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s13, 0x4f7ffffe
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
+; GFX6-NEXT: s_sub_i32 s2, 0, s8
+; GFX6-NEXT: s_sub_i32 s12, 0, s9
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s10
+; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s11
+; GFX6-NEXT: v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, s13, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mul_lo_u32 v4, s12, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v4, v1
+; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT: v_mul_f32_e32 v2, s13, v3
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s8
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s9
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT: s_sub_i32 s4, 0, s10
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_mul_lo_u32 v3, s4, v2
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s9, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v5
+; GFX6-NEXT: s_sub_i32 s4, 0, s11
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mul_f32_e32 v3, s13, v4
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s9, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, s6, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GFX6-NEXT: v_mul_lo_u32 v5, s4, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, s10
+; GFX6-NEXT: v_mul_hi_u32 v4, v3, v5
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s10, v2
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT: v_mul_hi_u32 v3, s7, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s10, v2
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, s11
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s7, v3
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s11, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s11, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_v4i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
+; GFX9-NEXT: s_mov_b32 s12, 0x4f7ffffe
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
+; GFX9-NEXT: s_sub_i32 s2, 0, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s10
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: s_sub_i32 s3, 0, s9
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; GFX9-NEXT: v_mul_f32_e32 v0, s12, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, s12, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s11
+; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
+; GFX9-NEXT: s_sub_i32 s2, 0, s10
+; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_f32_e32 v2, s12, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v6
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s2, v2
+; GFX9-NEXT: s_sub_i32 s2, 0, s11
+; GFX9-NEXT: v_mul_f32_e32 v3, s12, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_mul_hi_u32 v5, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s8
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, s2, v3
+; GFX9-NEXT: v_mul_hi_u32 v2, s6, v2
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s9
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
+; GFX9-NEXT: v_mul_hi_u32 v5, v3, v5
+; GFX9-NEXT: v_subrev_u32_e32 v6, s8, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, s7, v3
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, s10
+; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
+; GFX9-NEXT: v_subrev_u32_e32 v6, s8, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, s9, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v3, s11
+; GFX9-NEXT: v_sub_u32_e32 v2, s6, v2
+; GFX9-NEXT: v_subrev_u32_e32 v6, s9, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s10, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s10, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
+; GFX9-NEXT: v_sub_u32_e32 v3, s7, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s11, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s11, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-NEXT: s_endpgm
%r = urem <4 x i32> %x, %y
store <4 x i32> %r, <4 x i32> addrspace(1)* %out
ret void
@@ -1325,128 +1807,250 @@ define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x
; CHECK-NEXT: store <4 x i32> [[TMP164]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_v4i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s16, 0x4f7ffffe
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s2, s12, 31
-; GCN-NEXT: s_add_i32 s3, s12, s2
-; GCN-NEXT: s_xor_b32 s12, s3, s2
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12
-; GCN-NEXT: s_ashr_i32 s3, s13, 31
-; GCN-NEXT: s_add_i32 s0, s13, s3
-; GCN-NEXT: s_xor_b32 s13, s0, s3
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13
-; GCN-NEXT: s_sub_i32 s1, 0, s12
-; GCN-NEXT: s_ashr_i32 s0, s8, 31
-; GCN-NEXT: v_mul_f32_e32 v0, s16, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GCN-NEXT: s_xor_b32 s2, s0, s2
-; GCN-NEXT: v_mul_lo_u32 v2, s1, v0
-; GCN-NEXT: s_add_i32 s1, s8, s0
-; GCN-NEXT: v_mul_f32_e32 v1, s16, v1
-; GCN-NEXT: s_xor_b32 s1, s1, s0
-; GCN-NEXT: v_mul_hi_u32 v2, v0, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_sub_i32 s0, 0, s13
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
-; GCN-NEXT: v_mul_lo_u32 v2, s0, v1
-; GCN-NEXT: v_mul_lo_u32 v3, v0, s12
-; GCN-NEXT: v_mul_hi_u32 v2, v1, v2
-; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v0
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s1, v3
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v3
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s12, v3
-; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GCN-NEXT: v_xor_b32_e32 v0, s2, v0
-; GCN-NEXT: s_ashr_i32 s0, s9, 31
-; GCN-NEXT: s_add_i32 s1, s9, s0
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
-; GCN-NEXT: s_xor_b32 s2, s0, s3
-; GCN-NEXT: s_ashr_i32 s3, s14, 31
-; GCN-NEXT: s_xor_b32 s1, s1, s0
-; GCN-NEXT: s_add_i32 s0, s14, s3
-; GCN-NEXT: s_xor_b32 s9, s0, s3
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s9
-; GCN-NEXT: v_mul_hi_u32 v1, s1, v1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GCN-NEXT: v_mul_lo_u32 v2, v1, s13
-; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v1
-; GCN-NEXT: v_mul_f32_e32 v3, s16, v3
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v2
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s13, v2
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
-; GCN-NEXT: s_sub_i32 s0, 0, s9
-; GCN-NEXT: v_mul_lo_u32 v5, s0, v3
-; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v2
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GCN-NEXT: v_mul_hi_u32 v2, v3, v5
-; GCN-NEXT: v_xor_b32_e32 v1, s2, v1
-; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s2, v1
-; GCN-NEXT: s_ashr_i32 s2, s15, 31
-; GCN-NEXT: s_ashr_i32 s0, s10, 31
-; GCN-NEXT: s_add_i32 s8, s15, s2
-; GCN-NEXT: s_add_i32 s1, s10, s0
-; GCN-NEXT: s_xor_b32 s8, s8, s2
-; GCN-NEXT: v_cvt_f32_u32_e32 v4, s8
-; GCN-NEXT: s_xor_b32 s1, s1, s0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GCN-NEXT: v_mul_hi_u32 v2, s1, v2
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v4
-; GCN-NEXT: s_xor_b32 s3, s0, s3
-; GCN-NEXT: v_mul_lo_u32 v3, v2, s9
-; GCN-NEXT: v_mul_f32_e32 v4, s16, v4
-; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v2
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s1, v3
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v3
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s9, v3
-; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GCN-NEXT: s_sub_i32 s0, 0, s8
-; GCN-NEXT: v_mul_lo_u32 v5, s0, v4
-; GCN-NEXT: s_ashr_i32 s0, s11, 31
-; GCN-NEXT: s_add_i32 s1, s11, s0
-; GCN-NEXT: s_xor_b32 s1, s1, s0
-; GCN-NEXT: v_mul_hi_u32 v5, v4, v5
-; GCN-NEXT: v_add_i32_e32 v6, vcc, 1, v2
-; GCN-NEXT: s_xor_b32 s2, s0, s2
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_mul_hi_u32 v4, s1, v4
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
-; GCN-NEXT: v_xor_b32_e32 v2, s3, v2
-; GCN-NEXT: v_mul_lo_u32 v3, v4, s8
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v4
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s3, v2
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s1, v3
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3
-; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s8, v3
-; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v4
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
-; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
-; GCN-NEXT: v_xor_b32_e32 v3, s2, v3
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s2, v3
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_v4i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s16, 0x4f7ffffe
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s2, s12, 31
+; GFX6-NEXT: s_add_i32 s3, s12, s2
+; GFX6-NEXT: s_xor_b32 s12, s3, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12
+; GFX6-NEXT: s_ashr_i32 s3, s13, 31
+; GFX6-NEXT: s_add_i32 s0, s13, s3
+; GFX6-NEXT: s_xor_b32 s13, s0, s3
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13
+; GFX6-NEXT: s_sub_i32 s1, 0, s12
+; GFX6-NEXT: s_ashr_i32 s0, s8, 31
+; GFX6-NEXT: v_mul_f32_e32 v0, s16, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: s_xor_b32 s2, s0, s2
+; GFX6-NEXT: v_mul_lo_u32 v2, s1, v0
+; GFX6-NEXT: s_add_i32 s1, s8, s0
+; GFX6-NEXT: v_mul_f32_e32 v1, s16, v1
+; GFX6-NEXT: s_xor_b32 s1, s1, s0
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_sub_i32 s0, 0, s13
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, s12
+; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s1, v3
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s12, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX6-NEXT: s_ashr_i32 s0, s9, 31
+; GFX6-NEXT: s_add_i32 s1, s9, s0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT: s_xor_b32 s2, s0, s3
+; GFX6-NEXT: s_ashr_i32 s3, s14, 31
+; GFX6-NEXT: s_xor_b32 s1, s1, s0
+; GFX6-NEXT: s_add_i32 s0, s14, s3
+; GFX6-NEXT: s_xor_b32 s9, s0, s3
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s9
+; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, s13
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1
+; GFX6-NEXT: v_mul_f32_e32 v3, s16, v3
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s13, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
+; GFX6-NEXT: s_sub_i32 s0, 0, s9
+; GFX6-NEXT: v_mul_lo_u32 v5, s0, v3
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX6-NEXT: v_mul_hi_u32 v2, v3, v5
+; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s2, v1
+; GFX6-NEXT: s_ashr_i32 s2, s15, 31
+; GFX6-NEXT: s_ashr_i32 s0, s10, 31
+; GFX6-NEXT: s_add_i32 s8, s15, s2
+; GFX6-NEXT: s_add_i32 s1, s10, s0
+; GFX6-NEXT: s_xor_b32 s8, s8, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s8
+; GFX6-NEXT: s_xor_b32 s1, s1, s0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT: v_mul_hi_u32 v2, s1, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; GFX6-NEXT: s_xor_b32 s3, s0, s3
+; GFX6-NEXT: v_mul_lo_u32 v3, v2, s9
+; GFX6-NEXT: v_mul_f32_e32 v4, s16, v4
+; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s1, v3
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s9, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
+; GFX6-NEXT: s_sub_i32 s0, 0, s8
+; GFX6-NEXT: v_mul_lo_u32 v5, s0, v4
+; GFX6-NEXT: s_ashr_i32 s0, s11, 31
+; GFX6-NEXT: s_add_i32 s1, s11, s0
+; GFX6-NEXT: s_xor_b32 s1, s1, s0
+; GFX6-NEXT: v_mul_hi_u32 v5, v4, v5
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v2
+; GFX6-NEXT: s_xor_b32 s2, s0, s2
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT: v_mul_hi_u32 v4, s1, v4
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX6-NEXT: v_xor_b32_e32 v2, s3, v2
+; GFX6-NEXT: v_mul_lo_u32 v3, v4, s8
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s1, v3
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s8, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX6-NEXT: v_xor_b32_e32 v3, s2, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s2, v3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_v4i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
+; GFX9-NEXT: s_mov_b32 s13, 0x4f7ffffe
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s2, s8, 31
+; GFX9-NEXT: s_add_i32 s3, s8, s2
+; GFX9-NEXT: s_xor_b32 s14, s3, s2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s14
+; GFX9-NEXT: s_ashr_i32 s8, s9, 31
+; GFX9-NEXT: s_add_i32 s9, s9, s8
+; GFX9-NEXT: s_xor_b32 s15, s9, s8
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s15
+; GFX9-NEXT: s_sub_i32 s12, 0, s14
+; GFX9-NEXT: s_ashr_i32 s3, s4, 31
+; GFX9-NEXT: v_mul_f32_e32 v0, s13, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: s_add_i32 s4, s4, s3
+; GFX9-NEXT: s_xor_b32 s4, s4, s3
+; GFX9-NEXT: v_mul_lo_u32 v2, s12, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, s13, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_sub_i32 s12, 0, s15
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: s_ashr_i32 s9, s5, 31
+; GFX9-NEXT: v_mul_lo_u32 v3, s12, v1
+; GFX9-NEXT: s_xor_b32 s2, s3, s2
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX9-NEXT: v_mul_hi_u32 v2, v1, v3
+; GFX9-NEXT: s_add_i32 s3, s5, s9
+; GFX9-NEXT: s_xor_b32 s3, s3, s9
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, s14
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT: v_mul_hi_u32 v1, s3, v1
+; GFX9-NEXT: v_add_u32_e32 v2, 1, v0
+; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, s14, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v2
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, s15
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX9-NEXT: v_sub_u32_e32 v2, s3, v2
+; GFX9-NEXT: s_ashr_i32 s3, s10, 31
+; GFX9-NEXT: s_add_i32 s4, s10, s3
+; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0
+; GFX9-NEXT: s_xor_b32 s2, s9, s8
+; GFX9-NEXT: s_xor_b32 s9, s4, s3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s9
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_subrev_u32_e32 v5, s15, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: s_sub_i32 s4, 0, s9
+; GFX9-NEXT: v_mul_f32_e32 v3, s13, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v2
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s4, v3
+; GFX9-NEXT: s_ashr_i32 s4, s6, 31
+; GFX9-NEXT: s_add_i32 s5, s6, s4
+; GFX9-NEXT: s_ashr_i32 s6, s11, 31
+; GFX9-NEXT: s_add_i32 s8, s11, s6
+; GFX9-NEXT: s_xor_b32 s8, s8, s6
+; GFX9-NEXT: v_mul_hi_u32 v2, v3, v2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s8
+; GFX9-NEXT: s_xor_b32 s5, s5, s4
+; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v2, s5, v2
+; GFX9-NEXT: v_subrev_u32_e32 v1, s2, v1
+; GFX9-NEXT: s_xor_b32 s2, s4, s3
+; GFX9-NEXT: v_mul_f32_e32 v3, s13, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_mul_lo_u32 v5, v2, s9
+; GFX9-NEXT: s_sub_i32 s3, 0, s8
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v2
+; GFX9-NEXT: v_mul_lo_u32 v7, s3, v3
+; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, s9, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX9-NEXT: v_mul_hi_u32 v6, v3, v7
+; GFX9-NEXT: s_ashr_i32 s3, s7, 31
+; GFX9-NEXT: s_add_i32 s4, s7, s3
+; GFX9-NEXT: s_xor_b32 s4, s4, s3
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v6
+; GFX9-NEXT: v_mul_hi_u32 v3, s4, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, v3, s8
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
+; GFX9-NEXT: v_xor_b32_e32 v2, s2, v2
+; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v2
+; GFX9-NEXT: v_sub_u32_e32 v5, s4, v5
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, s8, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
+; GFX9-NEXT: s_xor_b32 s2, s3, s6
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: v_xor_b32_e32 v3, s2, v3
+; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v3
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-NEXT: s_endpgm
%r = sdiv <4 x i32> %x, %y
store <4 x i32> %r, <4 x i32> addrspace(1)* %out
ret void
@@ -1609,116 +2213,226 @@ define amdgpu_kernel void @srem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x
; CHECK-NEXT: store <4 x i32> [[TMP152]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_v4i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s13, 0x4f7ffffe
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s2, s8, 31
-; GCN-NEXT: s_add_i32 s8, s8, s2
-; GCN-NEXT: s_xor_b32 s12, s8, s2
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12
-; GCN-NEXT: s_ashr_i32 s8, s9, 31
-; GCN-NEXT: s_add_i32 s9, s9, s8
-; GCN-NEXT: s_xor_b32 s14, s9, s8
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s14
-; GCN-NEXT: s_sub_i32 s9, 0, s12
-; GCN-NEXT: s_ashr_i32 s8, s4, 31
-; GCN-NEXT: v_mul_f32_e32 v0, s13, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GCN-NEXT: s_add_i32 s4, s4, s8
-; GCN-NEXT: s_xor_b32 s4, s4, s8
-; GCN-NEXT: v_mul_lo_u32 v2, s9, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s13, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_sub_i32 s9, 0, s14
-; GCN-NEXT: v_mul_hi_u32 v2, v0, v2
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s4, v0
-; GCN-NEXT: v_mul_lo_u32 v2, s9, v1
-; GCN-NEXT: s_ashr_i32 s9, s5, 31
-; GCN-NEXT: s_add_i32 s5, s5, s9
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s12
-; GCN-NEXT: v_mul_hi_u32 v2, v1, v2
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GCN-NEXT: s_xor_b32 s4, s5, s9
-; GCN-NEXT: s_ashr_i32 s5, s10, 31
-; GCN-NEXT: s_add_i32 s10, s10, s5
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s12, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
-; GCN-NEXT: s_xor_b32 s10, s10, s5
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s10
-; GCN-NEXT: v_mul_hi_u32 v1, s4, v1
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s12, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s14
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GCN-NEXT: v_xor_b32_e32 v0, s8, v0
-; GCN-NEXT: v_mul_f32_e32 v2, s13, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
-; GCN-NEXT: s_sub_i32 s4, 0, s10
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s14, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s14, v1
-; GCN-NEXT: v_mul_lo_u32 v4, s4, v2
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s14, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s14, v1
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GCN-NEXT: v_mul_hi_u32 v3, v2, v4
-; GCN-NEXT: s_ashr_i32 s4, s6, 31
-; GCN-NEXT: s_add_i32 s5, s6, s4
-; GCN-NEXT: s_ashr_i32 s6, s11, 31
-; GCN-NEXT: s_add_i32 s8, s11, s6
-; GCN-NEXT: s_xor_b32 s8, s8, s6
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s8
-; GCN-NEXT: s_xor_b32 s5, s5, s4
-; GCN-NEXT: v_mul_hi_u32 v2, s5, v2
-; GCN-NEXT: v_xor_b32_e32 v1, s9, v1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s9, v1
-; GCN-NEXT: v_mul_lo_u32 v2, v2, s10
-; GCN-NEXT: v_mul_f32_e32 v3, s13, v3
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s5, v2
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s10, v2
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
-; GCN-NEXT: s_sub_i32 s5, 0, s8
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v4, s5, v3
-; GCN-NEXT: s_ashr_i32 s5, s7, 31
-; GCN-NEXT: s_add_i32 s6, s7, s5
-; GCN-NEXT: s_xor_b32 s6, s6, s5
-; GCN-NEXT: v_mul_hi_u32 v4, v3, v4
-; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s10, v2
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT: v_mul_hi_u32 v3, s6, v3
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
-; GCN-NEXT: v_xor_b32_e32 v2, s4, v2
-; GCN-NEXT: v_mul_lo_u32 v3, v3, s8
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s4, v2
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s6, v3
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: v_xor_b32_e32 v3, s5, v3
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s5, v3
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_v4i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s13, 0x4f7ffffe
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s2, s8, 31
+; GFX6-NEXT: s_add_i32 s8, s8, s2
+; GFX6-NEXT: s_xor_b32 s12, s8, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12
+; GFX6-NEXT: s_ashr_i32 s8, s9, 31
+; GFX6-NEXT: s_add_i32 s9, s9, s8
+; GFX6-NEXT: s_xor_b32 s14, s9, s8
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s14
+; GFX6-NEXT: s_sub_i32 s9, 0, s12
+; GFX6-NEXT: s_ashr_i32 s8, s4, 31
+; GFX6-NEXT: v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: s_add_i32 s4, s4, s8
+; GFX6-NEXT: s_xor_b32 s4, s4, s8
+; GFX6-NEXT: v_mul_lo_u32 v2, s9, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, s13, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_sub_i32 s9, 0, s14
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, s9, v1
+; GFX6-NEXT: s_ashr_i32 s9, s5, 31
+; GFX6-NEXT: s_add_i32 s5, s5, s9
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s12
+; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: s_xor_b32 s4, s5, s9
+; GFX6-NEXT: s_ashr_i32 s5, s10, 31
+; GFX6-NEXT: s_add_i32 s10, s10, s5
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s12, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
+; GFX6-NEXT: s_xor_b32 s10, s10, s5
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s10
+; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s12, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s14
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0
+; GFX6-NEXT: v_mul_f32_e32 v2, s13, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
+; GFX6-NEXT: s_sub_i32 s4, 0, s10
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s14, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v1
+; GFX6-NEXT: v_mul_lo_u32 v4, s4, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s14, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_mul_hi_u32 v3, v2, v4
+; GFX6-NEXT: s_ashr_i32 s4, s6, 31
+; GFX6-NEXT: s_add_i32 s5, s6, s4
+; GFX6-NEXT: s_ashr_i32 s6, s11, 31
+; GFX6-NEXT: s_add_i32 s8, s11, s6
+; GFX6-NEXT: s_xor_b32 s8, s8, s6
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s8
+; GFX6-NEXT: s_xor_b32 s5, s5, s4
+; GFX6-NEXT: v_mul_hi_u32 v2, s5, v2
+; GFX6-NEXT: v_xor_b32_e32 v1, s9, v1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s9, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, s10
+; GFX6-NEXT: v_mul_f32_e32 v3, s13, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s5, v2
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s10, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
+; GFX6-NEXT: s_sub_i32 s5, 0, s8
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v4, s5, v3
+; GFX6-NEXT: s_ashr_i32 s5, s7, 31
+; GFX6-NEXT: s_add_i32 s6, s7, s5
+; GFX6-NEXT: s_xor_b32 s6, s6, s5
+; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s10, v2
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT: v_mul_hi_u32 v3, s6, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_xor_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, s8
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s4, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s6, v3
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s8, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX6-NEXT: v_xor_b32_e32 v3, s5, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s5, v3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_v4i32:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
+; GFX9-NEXT: s_mov_b32 s13, 0x4f7ffffe
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s2, s8, 31
+; GFX9-NEXT: s_add_i32 s8, s8, s2
+; GFX9-NEXT: s_xor_b32 s2, s8, s2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GFX9-NEXT: s_ashr_i32 s3, s9, 31
+; GFX9-NEXT: s_sub_i32 s12, 0, s2
+; GFX9-NEXT: s_add_i32 s8, s9, s3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: s_xor_b32 s3, s8, s3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s3
+; GFX9-NEXT: s_ashr_i32 s8, s4, 31
+; GFX9-NEXT: v_mul_f32_e32 v0, s13, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: s_add_i32 s4, s4, s8
+; GFX9-NEXT: s_xor_b32 s4, s4, s8
+; GFX9-NEXT: v_mul_lo_u32 v2, s12, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, s13, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_sub_i32 s12, 0, s3
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: s_ashr_i32 s9, s5, 31
+; GFX9-NEXT: v_mul_lo_u32 v3, s12, v1
+; GFX9-NEXT: s_add_i32 s5, s5, s9
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: s_xor_b32 s5, s5, s9
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
+; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
+; GFX9-NEXT: s_ashr_i32 s2, s10, 31
+; GFX9-NEXT: s_add_i32 s4, s10, s2
+; GFX9-NEXT: s_xor_b32 s2, s4, s2
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX9-NEXT: s_sub_i32 s4, 0, s2
+; GFX9-NEXT: v_xor_b32_e32 v0, s8, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
+; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: v_mul_f32_e32 v2, s13, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, s4, v2
+; GFX9-NEXT: s_ashr_i32 s4, s11, 31
+; GFX9-NEXT: s_add_i32 s5, s11, s4
+; GFX9-NEXT: s_xor_b32 s4, s5, s4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s4
+; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
+; GFX9-NEXT: s_ashr_i32 s3, s6, 31
+; GFX9-NEXT: s_add_i32 s5, s6, s3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
+; GFX9-NEXT: s_xor_b32 s5, s5, s3
+; GFX9-NEXT: v_mul_hi_u32 v2, s5, v2
+; GFX9-NEXT: v_mul_f32_e32 v3, s13, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: s_sub_i32 s6, 0, s4
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, s2
+; GFX9-NEXT: v_xor_b32_e32 v1, s9, v1
+; GFX9-NEXT: v_mul_lo_u32 v5, s6, v3
+; GFX9-NEXT: v_subrev_u32_e32 v0, s8, v0
+; GFX9-NEXT: v_sub_u32_e32 v2, s5, v2
+; GFX9-NEXT: s_ashr_i32 s5, s7, 31
+; GFX9-NEXT: v_mul_hi_u32 v5, v3, v5
+; GFX9-NEXT: s_add_i32 s6, s7, s5
+; GFX9-NEXT: s_xor_b32 s6, s6, s5
+; GFX9-NEXT: v_subrev_u32_e32 v6, s2, v2
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, s6, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s2, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, v3, s4
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: v_xor_b32_e32 v2, s3, v2
+; GFX9-NEXT: v_sub_u32_e32 v3, s6, v3
+; GFX9-NEXT: v_subrev_u32_e32 v5, s4, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s4, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_xor_b32_e32 v3, s5, v3
+; GFX9-NEXT: v_subrev_u32_e32 v1, s9, v1
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v2
+; GFX9-NEXT: v_subrev_u32_e32 v3, s5, v3
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-NEXT: s_endpgm
%r = srem <4 x i32> %x, %y
store <4 x i32> %r, <4 x i32> addrspace(1)* %out
ret void
@@ -1809,66 +2523,125 @@ define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x
; CHECK-NEXT: store <4 x i16> [[TMP80]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_v4i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s8, 0xffff
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_and_b32 s9, s2, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9
-; GCN-NEXT: s_lshr_b32 s9, s0, 16
-; GCN-NEXT: s_and_b32 s0, s0, s8
-; GCN-NEXT: s_lshr_b32 s2, s2, 16
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s2
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: v_cvt_f32_u32_e32 v4, s9
-; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3
-; GCN-NEXT: s_and_b32 s2, s3, s8
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT: v_mul_f32_e32 v1, v4, v5
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT: v_mad_f32 v2, -v1, v3, v4
-; GCN-NEXT: v_cvt_f32_u32_e32 v4, s2
-; GCN-NEXT: s_lshr_b32 s0, s1, 16
-; GCN-NEXT: s_and_b32 s1, s1, s8
-; GCN-NEXT: s_lshr_b32 s10, s3, 16
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s10
-; GCN-NEXT: v_cvt_f32_u32_e32 v5, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v1, vcc
-; GCN-NEXT: v_rcp_iflag_f32_e32 v7, v3
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GCN-NEXT: v_mul_f32_e32 v1, v5, v6
-; GCN-NEXT: v_cvt_f32_u32_e32 v6, s0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mad_f32 v5, -v1, v4, v5
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, v4
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mul_f32_e32 v4, v6, v7
-; GCN-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-NEXT: v_cvt_u32_f32_e32 v5, v4
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mad_f32 v4, -v4, v3, v6
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT: v_and_b32_e32 v0, s8, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GCN-NEXT: v_and_b32_e32 v1, s8, v1
-; GCN-NEXT: v_or_b32_e32 v1, v1, v3
-; GCN-NEXT: v_or_b32_e32 v0, v0, v2
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_v4i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s8, 0xffff
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s9, s2, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s9
+; GFX6-NEXT: s_lshr_b32 s9, s0, 16
+; GFX6-NEXT: s_and_b32 s0, s0, s8
+; GFX6-NEXT: s_lshr_b32 s2, s2, 16
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s9
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3
+; GFX6-NEXT: s_and_b32 s2, s3, s8
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, v4, v5
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GFX6-NEXT: v_mad_f32 v2, -v1, v3, v4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s2
+; GFX6-NEXT: s_lshr_b32 s0, s1, 16
+; GFX6-NEXT: s_and_b32 s1, s1, s8
+; GFX6-NEXT: s_lshr_b32 s10, s3, 16
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s10
+; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v1, vcc
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_mul_f32_e32 v1, v5, v6
+; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mad_f32 v5, -v1, v4, v5
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, v4
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_f32_e32 v4, v6, v7
+; GFX6-NEXT: v_trunc_f32_e32 v4, v4
+; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v4
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mad_f32 v4, -v4, v3, v6
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX6-NEXT: v_and_b32_e32 v1, s8, v1
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_v4i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX9-NEXT: s_mov_b32 s8, 0xffff
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s1, s6, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s1
+; GFX9-NEXT: s_lshr_b32 s0, s4, 16
+; GFX9-NEXT: s_and_b32 s4, s4, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s4
+; GFX9-NEXT: s_lshr_b32 s4, s6, 16
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s0
+; GFX9-NEXT: s_and_b32 s0, s7, s8
+; GFX9-NEXT: v_mul_f32_e32 v3, v1, v3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, v5, v6
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mad_f32 v3, -v1, v4, v5
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s0
+; GFX9-NEXT: s_and_b32 s0, s5, s8
+; GFX9-NEXT: s_lshr_b32 s6, s7, 16
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s6
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v5
+; GFX9-NEXT: s_lshr_b32 s1, s5, 16
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v4
+; GFX9-NEXT: v_mul_f32_e32 v1, v6, v7
+; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s1
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_mad_f32 v6, -v1, v5, v6
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_f32_e32 v5, v7, v8
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mad_f32 v5, -v5, v4, v7
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, v4
+; GFX9-NEXT: v_mov_b32_e32 v5, 0xffff
+; GFX9-NEXT: v_and_b32_e32 v0, v5, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
+; GFX9-NEXT: v_and_b32_e32 v1, v5, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v4, 16, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = udiv <4 x i16> %x, %y
store <4 x i16> %r, <4 x i16> addrspace(1)* %out
ret void
@@ -1967,74 +2740,141 @@ define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x
; CHECK-NEXT: store <4 x i16> [[TMP88]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_v4i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s8, 0xffff
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_and_b32 s9, s2, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9
-; GCN-NEXT: s_and_b32 s10, s0, s8
-; GCN-NEXT: s_lshr_b32 s11, s2, 16
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s10
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s11
-; GCN-NEXT: s_lshr_b32 s9, s0, 16
-; GCN-NEXT: v_cvt_f32_u32_e32 v4, s9
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT: v_mul_f32_e32 v1, v4, v5
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GCN-NEXT: v_mad_f32 v1, -v1, v3, v4
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v3
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
-; GCN-NEXT: s_and_b32 s2, s3, s8
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GCN-NEXT: s_and_b32 s2, s1, s8
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s11
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s2
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
-; GCN-NEXT: s_lshr_b32 s12, s3, 16
-; GCN-NEXT: v_sub_i32_e32 v5, vcc, s9, v1
-; GCN-NEXT: s_lshr_b32 s10, s1, 16
-; GCN-NEXT: v_mul_f32_e32 v1, v3, v4
-; GCN-NEXT: v_cvt_f32_u32_e32 v4, s12
-; GCN-NEXT: v_cvt_f32_u32_e32 v6, s10
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v7, v4
-; GCN-NEXT: v_mad_f32 v3, -v1, v2, v3
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mul_f32_e32 v2, v6, v7
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mad_f32 v2, -v2, v4, v6
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s3
-; GCN-NEXT: v_mul_lo_u32 v2, v2, s12
-; GCN-NEXT: v_and_b32_e32 v0, s8, v0
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s10, v2
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GCN-NEXT: v_and_b32_e32 v1, s8, v1
-; GCN-NEXT: v_or_b32_e32 v1, v1, v2
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v5
-; GCN-NEXT: v_or_b32_e32 v0, v0, v2
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_v4i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s8, 0xffff
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s9, s2, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s9
+; GFX6-NEXT: s_and_b32 s10, s0, s8
+; GFX6-NEXT: s_lshr_b32 s11, s2, 16
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s10
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s11
+; GFX6-NEXT: s_lshr_b32 s9, s0, 16
+; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s9
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, v4, v5
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1
+; GFX6-NEXT: v_mad_f32 v1, -v1, v3, v4
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v3
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT: s_and_b32 s2, s3, s8
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GFX6-NEXT: s_and_b32 s2, s1, s8
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s11
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v2
+; GFX6-NEXT: s_lshr_b32 s12, s3, 16
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s9, v1
+; GFX6-NEXT: s_lshr_b32 s10, s1, 16
+; GFX6-NEXT: v_mul_f32_e32 v1, v3, v4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s12
+; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s10
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v4
+; GFX6-NEXT: v_mad_f32 v3, -v1, v2, v3
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_f32_e32 v2, v6, v7
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mad_f32 v2, -v2, v4, v6
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, s12
+; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s10, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_and_b32_e32 v1, s8, v1
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_v4i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX9-NEXT: s_mov_b32 s8, 0xffff
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s1, s6, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s1
+; GFX9-NEXT: s_and_b32 s9, s4, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
+; GFX9-NEXT: s_lshr_b32 s9, s6, 16
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s9
+; GFX9-NEXT: s_lshr_b32 s0, s4, 16
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s0
+; GFX9-NEXT: v_mul_f32_e32 v3, v1, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX9-NEXT: s_lshr_b32 s10, s7, 16
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mul_f32_e32 v1, v5, v6
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s6
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: s_and_b32 s6, s7, s8
+; GFX9-NEXT: v_mad_f32 v3, -v1, v4, v5
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s6
+; GFX9-NEXT: s_and_b32 s6, s5, s8
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s10
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s6
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_lshr_b32 s1, s5, 16
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v4
+; GFX9-NEXT: v_mul_f32_e32 v3, v6, v7
+; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s1
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mad_f32 v6, -v3, v5, v6
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_mul_f32_e32 v5, v7, v8
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mad_f32 v5, -v5, v4, v7
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s9
+; GFX9-NEXT: v_mul_lo_u32 v3, v3, s7
+; GFX9-NEXT: v_mul_lo_u32 v4, v4, s10
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
+; GFX9-NEXT: v_sub_u32_e32 v5, s0, v1
+; GFX9-NEXT: v_sub_u32_e32 v1, s5, v3
+; GFX9-NEXT: v_sub_u32_e32 v3, s1, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
+; GFX9-NEXT: v_and_b32_e32 v1, v4, v1
+; GFX9-NEXT: v_and_b32_e32 v0, v4, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v5, 16, v0
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = urem <4 x i16> %x, %y
store <4 x i16> %r, <4 x i16> addrspace(1)* %out
ret void
@@ -2141,86 +2981,164 @@ define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x
; CHECK-NEXT: store <4 x i16> [[TMP96]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_v4i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_sext_i32_i16 s8, s2
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
-; GCN-NEXT: s_sext_i32_i16 s9, s0
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s9
-; GCN-NEXT: s_xor_b32 s8, s9, s8
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_ashr_i32 s2, s2, 16
-; GCN-NEXT: s_ashr_i32 s8, s8, 30
-; GCN-NEXT: s_or_b32 s8, s8, 1
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s2
-; GCN-NEXT: v_mov_b32_e32 v3, s8
-; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GCN-NEXT: s_ashr_i32 s0, s0, 16
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v1
-; GCN-NEXT: s_xor_b32 s0, s0, s2
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mul_f32_e32 v3, v2, v3
-; GCN-NEXT: v_trunc_f32_e32 v3, v3
-; GCN-NEXT: v_mad_f32 v2, -v3, v1, v2
-; GCN-NEXT: v_mov_b32_e32 v4, s0
-; GCN-NEXT: s_sext_i32_i16 s0, s3
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1|
-; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3
-; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0
-; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
-; GCN-NEXT: s_sext_i32_i16 s2, s1
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v1, v3
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s2
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
-; GCN-NEXT: s_xor_b32 s0, s2, s0
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mul_f32_e32 v4, v1, v4
-; GCN-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-NEXT: v_mad_f32 v1, -v4, v2, v1
-; GCN-NEXT: v_mov_b32_e32 v5, s0
-; GCN-NEXT: s_ashr_i32 s0, s3, 16
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v2|
-; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4
-; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0
-; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
-; GCN-NEXT: s_ashr_i32 s1, s1, 16
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4
-; GCN-NEXT: v_cvt_f32_i32_e32 v4, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v2
-; GCN-NEXT: s_xor_b32 s0, s1, s0
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mul_f32_e32 v5, v4, v5
-; GCN-NEXT: v_trunc_f32_e32 v5, v5
-; GCN-NEXT: v_mad_f32 v4, -v5, v2, v4
-; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5
-; GCN-NEXT: v_mov_b32_e32 v6, s0
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2|
-; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; GCN-NEXT: s_mov_b32 s0, 0xffff
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GCN-NEXT: v_and_b32_e32 v1, s0, v1
-; GCN-NEXT: v_or_b32_e32 v1, v1, v2
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GCN-NEXT: v_and_b32_e32 v0, s0, v0
-; GCN-NEXT: v_or_b32_e32 v0, v0, v2
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_v4i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_sext_i32_i16 s8, s2
+; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s8
+; GFX6-NEXT: s_sext_i32_i16 s9, s0
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s9
+; GFX6-NEXT: s_xor_b32 s8, s9, s8
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_ashr_i32 s2, s2, 16
+; GFX6-NEXT: s_ashr_i32 s8, s8, 30
+; GFX6-NEXT: s_or_b32 s8, s8, 1
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s2
+; GFX6-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: s_ashr_i32 s0, s0, 16
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v1
+; GFX6-NEXT: s_xor_b32 s0, s0, s2
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v3
+; GFX6-NEXT: v_mad_f32 v2, -v3, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v4, s0
+; GFX6-NEXT: s_sext_i32_i16 s0, s3
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1|
+; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s0
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
+; GFX6-NEXT: s_sext_i32_i16 s2, s1
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v1, v3
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v2
+; GFX6-NEXT: s_xor_b32 s0, s2, s0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mul_f32_e32 v4, v1, v4
+; GFX6-NEXT: v_trunc_f32_e32 v4, v4
+; GFX6-NEXT: v_mad_f32 v1, -v4, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v5, s0
+; GFX6-NEXT: s_ashr_i32 s0, s3, 16
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v2|
+; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s0
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX6-NEXT: s_ashr_i32 s1, s1, 16
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
+; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v2
+; GFX6-NEXT: s_xor_b32 s0, s1, s0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v5
+; GFX6-NEXT: v_mad_f32 v4, -v5, v2, v4
+; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX6-NEXT: v_mov_b32_e32 v6, s0
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2|
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT: s_mov_b32 s0, 0xffff
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_v4i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_sext_i32_i16 s0, s6
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s0
+; GFX9-NEXT: s_sext_i32_i16 s1, s4
+; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s1
+; GFX9-NEXT: s_xor_b32 s0, s1, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s8, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v3, v1, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v1
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s8, 0
+; GFX9-NEXT: s_ashr_i32 s1, s6, 16
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s1
+; GFX9-NEXT: s_ashr_i32 s4, s4, 16
+; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s4
+; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v0
+; GFX9-NEXT: v_add_u32_e32 v3, s0, v3
+; GFX9-NEXT: v_mul_f32_e32 v4, v1, v4
+; GFX9-NEXT: s_xor_b32 s0, s4, s1
+; GFX9-NEXT: v_trunc_f32_e32 v4, v4
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: v_mad_f32 v1, -v4, v0, v1
+; GFX9-NEXT: s_or_b32 s4, s0, 1
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_sext_i32_i16 s1, s7
+; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s1
+; GFX9-NEXT: s_cselect_b32 s0, s4, 0
+; GFX9-NEXT: v_add_u32_e32 v4, s0, v4
+; GFX9-NEXT: s_sext_i32_i16 s0, s5
+; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v0
+; GFX9-NEXT: s_xor_b32 s0, s0, s1
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s4, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v5, v1, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_mad_f32 v1, -v5, v0, v1
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s4, 0
+; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX9-NEXT: s_ashr_i32 s1, s7, 16
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s1
+; GFX9-NEXT: v_add_u32_e32 v1, s0, v5
+; GFX9-NEXT: s_ashr_i32 s0, s5, 16
+; GFX9-NEXT: v_cvt_f32_i32_e32 v5, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v0
+; GFX9-NEXT: s_xor_b32 s0, s0, s1
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s4, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v6, v5, v6
+; GFX9-NEXT: v_trunc_f32_e32 v6, v6
+; GFX9-NEXT: v_mad_f32 v5, -v6, v0, v5
+; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v6
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s4, 0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0xffff
+; GFX9-NEXT: v_add_u32_e32 v0, s0, v6
+; GFX9-NEXT: v_and_b32_e32 v1, v5, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v0, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v0, v5, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v4, 16, v0
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = sdiv <4 x i16> %x, %y
store <4 x i16> %r, <4 x i16> addrspace(1)* %out
ret void
@@ -2335,94 +3253,180 @@ define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x
; CHECK-NEXT: store <4 x i16> [[TMP104]], <4 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_v4i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_sext_i32_i16 s8, s2
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
-; GCN-NEXT: s_sext_i32_i16 s9, s0
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s9
-; GCN-NEXT: s_xor_b32 s8, s9, s8
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_ashr_i32 s8, s8, 30
-; GCN-NEXT: s_or_b32 s8, s8, 1
-; GCN-NEXT: v_mov_b32_e32 v3, s8
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
-; GCN-NEXT: s_ashr_i32 s2, s2, 16
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s2
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: s_ashr_i32 s0, s0, 16
-; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v1
-; GCN-NEXT: s_xor_b32 s8, s0, s2
-; GCN-NEXT: s_ashr_i32 s8, s8, 30
-; GCN-NEXT: s_or_b32 s8, s8, 1
-; GCN-NEXT: v_mul_f32_e32 v3, v2, v3
-; GCN-NEXT: v_trunc_f32_e32 v3, v3
-; GCN-NEXT: v_mad_f32 v2, -v3, v1, v2
-; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3
-; GCN-NEXT: v_mov_b32_e32 v4, s8
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1|
-; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s2
-; GCN-NEXT: s_sext_i32_i16 s2, s3
-; GCN-NEXT: v_cvt_f32_i32_e32 v2, s2
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s0, v1
-; GCN-NEXT: s_sext_i32_i16 s0, s1
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
-; GCN-NEXT: s_xor_b32 s0, s0, s2
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mul_f32_e32 v4, v1, v4
-; GCN-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-NEXT: v_mad_f32 v1, -v4, v2, v1
-; GCN-NEXT: v_mov_b32_e32 v5, s0
-; GCN-NEXT: s_ashr_i32 s0, s3, 16
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v2|
-; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4
-; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0
-; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
-; GCN-NEXT: s_ashr_i32 s2, s1, 16
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4
-; GCN-NEXT: v_cvt_f32_i32_e32 v4, s2
-; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v2
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s3
-; GCN-NEXT: s_xor_b32 s3, s2, s0
-; GCN-NEXT: s_ashr_i32 s3, s3, 30
-; GCN-NEXT: v_mul_f32_e32 v5, v4, v5
-; GCN-NEXT: v_trunc_f32_e32 v5, v5
-; GCN-NEXT: v_mad_f32 v4, -v5, v2, v4
-; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5
-; GCN-NEXT: s_or_b32 s3, s3, 1
-; GCN-NEXT: v_mov_b32_e32 v6, s3
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2|
-; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; GCN-NEXT: v_mul_lo_u32 v2, v2, s0
-; GCN-NEXT: s_mov_b32 s0, 0xffff
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
-; GCN-NEXT: v_and_b32_e32 v1, s0, v1
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GCN-NEXT: v_or_b32_e32 v1, v1, v2
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GCN-NEXT: v_and_b32_e32 v0, s0, v0
-; GCN-NEXT: v_or_b32_e32 v0, v0, v2
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_v4i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_sext_i32_i16 s8, s2
+; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s8
+; GFX6-NEXT: s_sext_i32_i16 s9, s0
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s9
+; GFX6-NEXT: s_xor_b32 s8, s9, s8
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_ashr_i32 s8, s8, 30
+; GFX6-NEXT: s_or_b32 s8, s8, 1
+; GFX6-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT: s_ashr_i32 s2, s2, 16
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s2
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 16
+; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v1
+; GFX6-NEXT: s_xor_b32 s8, s0, s2
+; GFX6-NEXT: s_ashr_i32 s8, s8, 30
+; GFX6-NEXT: s_or_b32 s8, s8, 1
+; GFX6-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v3
+; GFX6-NEXT: v_mad_f32 v2, -v3, v1, v2
+; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX6-NEXT: v_mov_b32_e32 v4, s8
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1|
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s2
+; GFX6-NEXT: s_sext_i32_i16 s2, s3
+; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s0, v1
+; GFX6-NEXT: s_sext_i32_i16 s0, s1
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v2
+; GFX6-NEXT: s_xor_b32 s0, s0, s2
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mul_f32_e32 v4, v1, v4
+; GFX6-NEXT: v_trunc_f32_e32 v4, v4
+; GFX6-NEXT: v_mad_f32 v1, -v4, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v5, s0
+; GFX6-NEXT: s_ashr_i32 s0, s3, 16
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v2|
+; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s0
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GFX6-NEXT: s_ashr_i32 s2, s1, 16
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
+; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v2
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX6-NEXT: s_xor_b32 s3, s2, s0
+; GFX6-NEXT: s_ashr_i32 s3, s3, 30
+; GFX6-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v5
+; GFX6-NEXT: v_mad_f32 v4, -v5, v2, v4
+; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX6-NEXT: s_or_b32 s3, s3, 1
+; GFX6-NEXT: v_mov_b32_e32 v6, s3
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2|
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, s0
+; GFX6-NEXT: s_mov_b32 s0, 0xffff
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
+; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_v4i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_sext_i32_i16 s0, s6
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s0
+; GFX9-NEXT: s_sext_i32_i16 s1, s4
+; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s1
+; GFX9-NEXT: s_xor_b32 s0, s1, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s8, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v3, v1, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v1
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s8, 0
+; GFX9-NEXT: s_ashr_i32 s9, s6, 16
+; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s9
+; GFX9-NEXT: s_ashr_i32 s8, s4, 16
+; GFX9-NEXT: v_add_u32_e32 v1, s0, v3
+; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s8
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v0
+; GFX9-NEXT: s_xor_b32 s0, s8, s9
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s6
+; GFX9-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX9-NEXT: v_trunc_f32_e32 v4, v4
+; GFX9-NEXT: v_mad_f32 v3, -v4, v0, v3
+; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX9-NEXT: s_or_b32 s6, s0, 1
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s6, 0
+; GFX9-NEXT: v_add_u32_e32 v0, s0, v4
+; GFX9-NEXT: s_sext_i32_i16 s0, s7
+; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s0
+; GFX9-NEXT: s_sext_i32_i16 s1, s5
+; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s1
+; GFX9-NEXT: s_xor_b32 s0, s1, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v3
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s6, s0, 1
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s9
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_mad_f32 v4, -v5, v3, v4
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX9-NEXT: s_cselect_b32 s0, s6, 0
+; GFX9-NEXT: s_ashr_i32 s6, s7, 16
+; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s6
+; GFX9-NEXT: v_add_u32_e32 v3, s0, v5
+; GFX9-NEXT: v_mul_lo_u32 v3, v3, s7
+; GFX9-NEXT: s_ashr_i32 s7, s5, 16
+; GFX9-NEXT: v_cvt_f32_i32_e32 v5, s7
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GFX9-NEXT: s_xor_b32 s0, s7, s6
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s9, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v6, v5, v6
+; GFX9-NEXT: v_trunc_f32_e32 v6, v6
+; GFX9-NEXT: v_mad_f32 v5, -v6, v4, v5
+; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v6
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, |v4|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s9, 0
+; GFX9-NEXT: v_add_u32_e32 v4, s0, v6
+; GFX9-NEXT: v_mul_lo_u32 v4, v4, s6
+; GFX9-NEXT: v_sub_u32_e32 v5, s4, v1
+; GFX9-NEXT: v_sub_u32_e32 v1, s5, v3
+; GFX9-NEXT: v_sub_u32_e32 v0, s8, v0
+; GFX9-NEXT: v_sub_u32_e32 v3, s7, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
+; GFX9-NEXT: v_and_b32_e32 v1, v4, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v3, v4, v5
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v3
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = srem <4 x i16> %x, %y
store <4 x i16> %r, <4 x i16> addrspace(1)* %out
ret void
@@ -2450,27 +3454,48 @@ define amdgpu_kernel void @udiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
; CHECK-NEXT: store i3 [[TMP17]], i3 addrspace(1)* [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_i3:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_bfe_u32 s1, s0, 0x30008
-; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-NEXT: s_and_b32 s0, s0, 7
-; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, s0
-; GCN-NEXT: v_mul_f32_e32 v1, v2, v1
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v1
-; GCN-NEXT: v_mad_f32 v1, -v1, v0, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GCN-NEXT: v_and_b32_e32 v0, 7, v0
-; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_i3:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_u32 s1, s0, 0x30008
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX6-NEXT: s_and_b32 s0, s0, 7
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s0
+; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v1
+; GFX6-NEXT: v_mad_f32 v1, -v1, v0, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GFX6-NEXT: v_and_b32_e32 v0, 7, v0
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_i3:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_bfe_u32 s0, s4, 0x30008
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX9-NEXT: s_and_b32 s0, s4, 7
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, s0
+; GFX9-NEXT: v_mul_f32_e32 v1, v3, v1
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v1
+; GFX9-NEXT: v_mad_f32 v1, -v1, v0, v3
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
+; GFX9-NEXT: v_and_b32_e32 v0, 7, v0
+; GFX9-NEXT: global_store_byte v2, v0, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = udiv i3 %x, %y
store i3 %r, i3 addrspace(1)* %out
ret void
@@ -2500,30 +3525,55 @@ define amdgpu_kernel void @urem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
; CHECK-NEXT: store i3 [[TMP19]], i3 addrspace(1)* [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_i3:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_bfe_u32 s1, s0, 0x30008
-; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-NEXT: s_and_b32 s2, s0, 7
-; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, s2
-; GCN-NEXT: s_lshr_b32 s1, s0, 8
-; GCN-NEXT: v_mul_f32_e32 v1, v2, v1
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v1
-; GCN-NEXT: v_mad_f32 v1, -v1, v0, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s1
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: v_and_b32_e32 v0, 7, v0
-; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_i3:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_u32 s1, s0, 0x30008
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX6-NEXT: s_and_b32 s2, s0, 7
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s2
+; GFX6-NEXT: s_lshr_b32 s1, s0, 8
+; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v1
+; GFX6-NEXT: v_mad_f32 v1, -v1, v0, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 7, v0
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_i3:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_bfe_u32 s3, s2, 0x30008
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, s3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0
+; GFX9-NEXT: s_and_b32 s4, s2, 7
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, s4
+; GFX9-NEXT: s_lshr_b32 s3, s2, 8
+; GFX9-NEXT: v_mul_f32_e32 v1, v2, v1
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v1
+; GFX9-NEXT: v_mad_f32 v1, -v1, v0, v2
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 7, v0
+; GFX9-NEXT: global_store_byte v1, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = urem i3 %x, %y
store i3 %r, i3 addrspace(1)* %out
ret void
@@ -2555,32 +3605,58 @@ define amdgpu_kernel void @sdiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
; CHECK-NEXT: store i3 [[TMP21]], i3 addrspace(1)* [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_i3:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_bfe_i32 s1, s0, 0x30008
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1
-; GCN-NEXT: s_bfe_i32 s0, s0, 0x30000
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0
-; GCN-NEXT: s_xor_b32 s0, s0, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mov_b32_e32 v3, s0
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_and_b32_e32 v0, 7, v0
-; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_i3:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_i32 s1, s0, 0x30008
+; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s1
+; GFX6-NEXT: s_bfe_i32 s0, s0, 0x30000
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s0
+; GFX6-NEXT: s_xor_b32 s0, s0, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mov_b32_e32 v3, s0
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_and_b32_e32 v0, 7, v0
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_i3:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_bfe_i32 s0, s4, 0x30008
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s0
+; GFX9-NEXT: s_bfe_i32 s1, s4, 0x30000
+; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s1
+; GFX9-NEXT: s_xor_b32 s0, s1, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s4, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s4, 0
+; GFX9-NEXT: v_add_u32_e32 v0, s0, v3
+; GFX9-NEXT: v_and_b32_e32 v0, 7, v0
+; GFX9-NEXT: global_store_byte v1, v0, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = sdiv i3 %x, %y
store i3 %r, i3 addrspace(1)* %out
ret void
@@ -2614,35 +3690,65 @@ define amdgpu_kernel void @srem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
; CHECK-NEXT: store i3 [[TMP23]], i3 addrspace(1)* [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_i3:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_bfe_i32 s1, s0, 0x30008
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1
-; GCN-NEXT: s_bfe_i32 s3, s0, 0x30000
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3
-; GCN-NEXT: s_xor_b32 s1, s3, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_ashr_i32 s1, s1, 30
-; GCN-NEXT: s_or_b32 s1, s1, 1
-; GCN-NEXT: v_mov_b32_e32 v3, s1
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GCN-NEXT: s_lshr_b32 s2, s0, 8
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: v_and_b32_e32 v0, 7, v0
-; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_i3:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_i32 s1, s0, 0x30008
+; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s1
+; GFX6-NEXT: s_bfe_i32 s3, s0, 0x30000
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s3
+; GFX6-NEXT: s_xor_b32 s1, s3, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_ashr_i32 s1, s1, 30
+; GFX6-NEXT: s_or_b32 s1, s1, 1
+; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: s_lshr_b32 s2, s0, 8
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 7, v0
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_i3:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_bfe_i32 s2, s4, 0x30008
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s2
+; GFX9-NEXT: s_bfe_i32 s3, s4, 0x30000
+; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s3
+; GFX9-NEXT: s_xor_b32 s2, s3, s2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX9-NEXT: s_ashr_i32 s2, s2, 30
+; GFX9-NEXT: s_lshr_b32 s5, s4, 8
+; GFX9-NEXT: s_or_b32 s6, s2, 1
+; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, v2
+; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX9-NEXT: s_cselect_b32 s2, s6, 0
+; GFX9-NEXT: v_add_u32_e32 v0, s2, v2
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 7, v0
+; GFX9-NEXT: global_store_byte v1, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%r = srem i3 %x, %y
store i3 %r, i3 addrspace(1)* %out
ret void
@@ -2713,54 +3819,101 @@ define amdgpu_kernel void @udiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x
; CHECK-NEXT: store <3 x i16> [[TMP60]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_v3i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s8, 0xffff
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_and_b32 s6, s0, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GCN-NEXT: s_and_b32 s6, s2, s8
-; GCN-NEXT: s_lshr_b32 s0, s0, 16
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s0
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s6
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_lshr_b32 s0, s2, 16
-; GCN-NEXT: v_cvt_f32_u32_e32 v4, s0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT: v_mul_f32_e32 v1, v4, v5
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: s_and_b32 s0, s1, s8
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT: v_mad_f32 v2, -v1, v3, v4
-; GCN-NEXT: v_cvt_f32_u32_e32 v4, s0
-; GCN-NEXT: s_and_b32 s0, s3, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v5, s0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mul_f32_e32 v2, v5, v6
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
-; GCN-NEXT: v_mad_f32 v2, -v2, v4, v5
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GCN-NEXT: v_and_b32_e32 v0, s8, v0
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
-; GCN-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_v3i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s8, 0xffff
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s6, s0, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GFX6-NEXT: s_and_b32 s6, s2, s8
+; GFX6-NEXT: s_lshr_b32 s0, s0, 16
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s0
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s6
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_lshr_b32 s0, s2, 16
+; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, v4, v5
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: s_and_b32 s0, s1, s8
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GFX6-NEXT: v_mad_f32 v2, -v1, v3, v4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s0
+; GFX6-NEXT: s_and_b32 s0, s3, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mul_f32_e32 v2, v5, v6
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX6-NEXT: v_mad_f32 v2, -v2, v4, v5
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_v3i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34
+; GFX9-NEXT: s_mov_b32 s8, 0xffff
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s0, s6, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s0
+; GFX9-NEXT: s_and_b32 s0, s4, s8
+; GFX9-NEXT: s_lshr_b32 s1, s6, 16
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s1
+; GFX9-NEXT: s_lshr_b32 s0, s4, 16
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s0
+; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
+; GFX9-NEXT: v_mul_f32_e32 v2, v5, v6
+; GFX9-NEXT: v_trunc_f32_e32 v2, v2
+; GFX9-NEXT: s_and_b32 s0, s7, s8
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mad_f32 v3, -v2, v4, v5
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s0
+; GFX9-NEXT: s_and_b32 s0, s5, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v5
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
+; GFX9-NEXT: v_mul_f32_e32 v3, v6, v7
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v3
+; GFX9-NEXT: v_mad_f32 v3, -v3, v5, v6
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: global_store_short v1, v3, s[2:3] offset:4
+; GFX9-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = udiv <3 x i16> %x, %y
store <3 x i16> %r, <3 x i16> addrspace(1)* %out
ret void
@@ -2837,64 +3990,117 @@ define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x
; CHECK-NEXT: store <3 x i16> [[TMP66]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_v3i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s8, 0xffff
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v1, s2
-; GCN-NEXT: s_and_b32 s6, s0, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GCN-NEXT: s_and_b32 s6, s2, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s6
-; GCN-NEXT: v_mov_b32_e32 v4, s0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0
-; GCN-NEXT: v_alignbit_b32 v4, s1, v4, 16
-; GCN-NEXT: v_and_b32_e32 v5, s8, v4
-; GCN-NEXT: v_alignbit_b32 v1, s3, v1, 16
-; GCN-NEXT: v_mul_f32_e32 v3, v2, v3
-; GCN-NEXT: v_trunc_f32_e32 v3, v3
-; GCN-NEXT: v_mad_f32 v2, -v3, v0, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, v5
-; GCN-NEXT: v_and_b32_e32 v3, s8, v1
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v6, vcc
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s0
-; GCN-NEXT: s_and_b32 s0, s1, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, v3
-; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v2
-; GCN-NEXT: v_cvt_f32_u32_e32 v6, s0
-; GCN-NEXT: s_and_b32 s0, s3, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v7, s0
-; GCN-NEXT: v_mul_f32_e32 v5, v3, v5
-; GCN-NEXT: v_trunc_f32_e32 v5, v5
-; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v6
-; GCN-NEXT: v_mad_f32 v3, -v5, v2, v3
-; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
-; GCN-NEXT: v_mul_f32_e32 v3, v7, v8
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GCN-NEXT: v_trunc_f32_e32 v3, v3
-; GCN-NEXT: v_mul_lo_u32 v2, v2, v4
-; GCN-NEXT: v_cvt_u32_f32_e32 v4, v3
-; GCN-NEXT: v_mad_f32 v3, -v3, v6, v7
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v6
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v3, v3, s1
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GCN-NEXT: v_and_b32_e32 v0, s8, v0
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s3, v3
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
-; GCN-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_v3i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s8, 0xffff
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-NEXT: s_and_b32 s6, s0, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GFX6-NEXT: s_and_b32 s6, s2, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s6
+; GFX6-NEXT: v_mov_b32_e32 v4, s0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX6-NEXT: v_alignbit_b32 v4, s1, v4, 16
+; GFX6-NEXT: v_and_b32_e32 v5, s8, v4
+; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 16
+; GFX6-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v3
+; GFX6-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v3
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, v5
+; GFX6-NEXT: v_and_b32_e32 v3, s8, v1
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v6, vcc
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s0
+; GFX6-NEXT: s_and_b32 s0, s1, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, v3
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s0
+; GFX6-NEXT: s_and_b32 s0, s3, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v7, s0
+; GFX6-NEXT: v_mul_f32_e32 v5, v3, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v5
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v6
+; GFX6-NEXT: v_mad_f32 v3, -v5, v2, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
+; GFX6-NEXT: v_mul_f32_e32 v3, v7, v8
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
+; GFX6-NEXT: v_trunc_f32_e32 v3, v3
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v3
+; GFX6-NEXT: v_mad_f32 v3, -v3, v6, v7
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v6
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, s1
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s3, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_v3i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34
+; GFX9-NEXT: s_mov_b32 s8, 0xffff
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s0, s4, s8
+; GFX9-NEXT: s_and_b32 s1, s6, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s1
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s0
+; GFX9-NEXT: s_lshr_b32 s6, s6, 16
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s6
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: s_lshr_b32 s4, s4, 16
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s4
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v2
+; GFX9-NEXT: v_mul_f32_e32 v3, v1, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v3
+; GFX9-NEXT: v_mad_f32 v1, -v3, v0, v1
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, v4, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s1
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: s_and_b32 s1, s7, s8
+; GFX9-NEXT: v_mad_f32 v3, -v1, v2, v4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s1
+; GFX9-NEXT: s_and_b32 s5, s5, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
+; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_f32_e32 v2, v5, v6
+; GFX9-NEXT: v_trunc_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2
+; GFX9-NEXT: v_mad_f32 v2, -v2, v4, v5
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s6
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, s1
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_sub_u32_e32 v2, s5, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: global_store_short v3, v2, s[2:3] offset:4
+; GFX9-NEXT: global_store_dword v3, v0, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = urem <3 x i16> %x, %y
store <3 x i16> %r, <3 x i16> addrspace(1)* %out
ret void
@@ -2977,68 +4183,129 @@ define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x
; CHECK-NEXT: store <3 x i16> [[TMP72]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_v3i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_sext_i32_i16 s9, s2
-; GCN-NEXT: s_sext_i32_i16 s8, s0
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s9
-; GCN-NEXT: s_xor_b32 s8, s9, s8
-; GCN-NEXT: s_ashr_i32 s0, s0, 16
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_ashr_i32 s8, s8, 30
-; GCN-NEXT: s_or_b32 s8, s8, 1
-; GCN-NEXT: v_mov_b32_e32 v3, s8
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0
-; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GCN-NEXT: s_ashr_i32 s2, s2, 16
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_cvt_f32_i32_e32 v2, s2
-; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v1
-; GCN-NEXT: s_xor_b32 s0, s2, s0
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mul_f32_e32 v3, v2, v3
-; GCN-NEXT: v_trunc_f32_e32 v3, v3
-; GCN-NEXT: v_mad_f32 v2, -v3, v1, v2
-; GCN-NEXT: v_mov_b32_e32 v4, s0
-; GCN-NEXT: s_sext_i32_i16 s0, s1
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1|
-; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3
-; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0
-; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
-; GCN-NEXT: s_sext_i32_i16 s1, s3
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_cvt_f32_i32_e32 v3, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
-; GCN-NEXT: s_xor_b32 s0, s1, s0
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mul_f32_e32 v4, v3, v4
-; GCN-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3
-; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4
-; GCN-NEXT: v_mov_b32_e32 v5, s0
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
-; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
-; GCN-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_v3i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_sext_i32_i16 s9, s2
+; GFX6-NEXT: s_sext_i32_i16 s8, s0
+; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s8
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s9
+; GFX6-NEXT: s_xor_b32 s8, s9, s8
+; GFX6-NEXT: s_ashr_i32 s0, s0, 16
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_ashr_i32 s8, s8, 30
+; GFX6-NEXT: s_or_b32 s8, s8, 1
+; GFX6-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: s_ashr_i32 s2, s2, 16
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v1
+; GFX6-NEXT: s_xor_b32 s0, s2, s0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX6-NEXT: v_trunc_f32_e32 v3, v3
+; GFX6-NEXT: v_mad_f32 v2, -v3, v1, v2
+; GFX6-NEXT: v_mov_b32_e32 v4, s0
+; GFX6-NEXT: s_sext_i32_i16 s0, s1
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1|
+; GFX6-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s0
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
+; GFX6-NEXT: s_sext_i32_i16 s1, s3
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v2
+; GFX6-NEXT: s_xor_b32 s0, s1, s0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX6-NEXT: v_trunc_f32_e32 v4, v4
+; GFX6-NEXT: v_mad_f32 v3, -v4, v2, v3
+; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX6-NEXT: v_mov_b32_e32 v5, s0
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_v3i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_sext_i32_i16 s1, s4
+; GFX9-NEXT: s_sext_i32_i16 s0, s6
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s0
+; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s1
+; GFX9-NEXT: s_xor_b32 s0, s1, s0
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: s_or_b32 s8, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s8, 0
+; GFX9-NEXT: s_ashr_i32 s1, s6, 16
+; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s1
+; GFX9-NEXT: s_ashr_i32 s4, s4, 16
+; GFX9-NEXT: v_add_u32_e32 v2, s0, v3
+; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s4
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v0
+; GFX9-NEXT: s_xor_b32 s0, s4, s1
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s4, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX9-NEXT: v_trunc_f32_e32 v4, v4
+; GFX9-NEXT: v_mad_f32 v3, -v4, v0, v3
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_sext_i32_i16 s1, s7
+; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s1
+; GFX9-NEXT: s_cselect_b32 s0, s4, 0
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_add_u32_e32 v3, s0, v4
+; GFX9-NEXT: s_sext_i32_i16 s0, s5
+; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v0
+; GFX9-NEXT: s_xor_b32 s0, s0, s1
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s4, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_mad_f32 v4, -v5, v0, v4
+; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s4, 0
+; GFX9-NEXT: v_add_u32_e32 v0, s0, v5
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: global_store_short v1, v0, s[2:3] offset:4
+; GFX9-NEXT: global_store_dword v1, v2, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = sdiv <3 x i16> %x, %y
store <3 x i16> %r, <3 x i16> addrspace(1)* %out
ret void
@@ -3127,77 +4394,144 @@ define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x
; CHECK-NEXT: store <3 x i16> [[TMP78]], <3 x i16> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_v3i16:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_sext_i32_i16 s8, s2
-; GCN-NEXT: s_sext_i32_i16 s6, s0
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s8
-; GCN-NEXT: s_xor_b32 s6, s8, s6
-; GCN-NEXT: s_ashr_i32 s6, s6, 30
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_or_b32 s6, s6, 1
-; GCN-NEXT: v_mov_b32_e32 v3, s6
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
-; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GCN-NEXT: v_mov_b32_e32 v1, s2
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_mov_b32_e32 v2, s0
-; GCN-NEXT: v_alignbit_b32 v2, s1, v2, 16
-; GCN-NEXT: v_bfe_i32 v3, v2, 0, 16
-; GCN-NEXT: v_cvt_f32_i32_e32 v4, v3
-; GCN-NEXT: v_alignbit_b32 v1, s3, v1, 16
-; GCN-NEXT: v_bfe_i32 v5, v1, 0, 16
-; GCN-NEXT: v_cvt_f32_i32_e32 v6, v5
-; GCN-NEXT: v_rcp_iflag_f32_e32 v7, v4
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s0
-; GCN-NEXT: v_xor_b32_e32 v3, v5, v3
-; GCN-NEXT: s_sext_i32_i16 s0, s1
-; GCN-NEXT: v_mul_f32_e32 v5, v6, v7
-; GCN-NEXT: v_trunc_f32_e32 v5, v5
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
-; GCN-NEXT: v_mad_f32 v6, -v5, v4, v6
-; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5
-; GCN-NEXT: v_ashrrev_i32_e32 v3, 30, v3
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, |v4|
-; GCN-NEXT: v_cvt_f32_i32_e32 v4, s0
-; GCN-NEXT: v_or_b32_e32 v3, 1, v3
-; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT: s_sext_i32_i16 s2, s3
-; GCN-NEXT: v_mul_lo_u32 v2, v3, v2
-; GCN-NEXT: v_cvt_f32_i32_e32 v3, s2
-; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v4
-; GCN-NEXT: s_xor_b32 s0, s2, s0
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mul_f32_e32 v5, v3, v5
-; GCN-NEXT: v_trunc_f32_e32 v5, v5
-; GCN-NEXT: v_mad_f32 v3, -v5, v4, v3
-; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5
-; GCN-NEXT: v_mov_b32_e32 v6, s0
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v4|
-; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT: v_mul_lo_u32 v3, v3, s1
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s3, v3
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
-; GCN-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_v3i16:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_sext_i32_i16 s8, s2
+; GFX6-NEXT: s_sext_i32_i16 s6, s0
+; GFX6-NEXT: v_cvt_f32_i32_e32 v0, s6
+; GFX6-NEXT: v_cvt_f32_i32_e32 v1, s8
+; GFX6-NEXT: s_xor_b32 s6, s8, s6
+; GFX6-NEXT: s_ashr_i32 s6, s6, 30
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT: s_or_b32 s6, s6, 1
+; GFX6-NEXT: v_mov_b32_e32 v3, s6
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT: v_trunc_f32_e32 v2, v2
+; GFX6-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-NEXT: v_alignbit_b32 v2, s1, v2, 16
+; GFX6-NEXT: v_bfe_i32 v3, v2, 0, 16
+; GFX6-NEXT: v_cvt_f32_i32_e32 v4, v3
+; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 16
+; GFX6-NEXT: v_bfe_i32 v5, v1, 0, 16
+; GFX6-NEXT: v_cvt_f32_i32_e32 v6, v5
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v4
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s0
+; GFX6-NEXT: v_xor_b32_e32 v3, v5, v3
+; GFX6-NEXT: s_sext_i32_i16 s0, s1
+; GFX6-NEXT: v_mul_f32_e32 v5, v6, v7
+; GFX6-NEXT: v_trunc_f32_e32 v5, v5
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT: v_mad_f32 v6, -v5, v4, v6
+; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, 30, v3
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, |v4|
+; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s0
+; GFX6-NEXT: v_or_b32_e32 v3, 1, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: s_sext_i32_i16 s2, s3
+; GFX6-NEXT: v_mul_lo_u32 v2, v3, v2
+; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v4
+; GFX6-NEXT: s_xor_b32 s0, s2, s0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mul_f32_e32 v5, v3, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v5
+; GFX6-NEXT: v_mad_f32 v3, -v5, v4, v3
+; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX6-NEXT: v_mov_b32_e32 v6, s0
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v4|
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, s1
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s3, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_v3i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x2c
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_sext_i32_i16 s8, s2
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s8
+; GFX9-NEXT: s_sext_i32_i16 s9, s6
+; GFX9-NEXT: v_cvt_f32_i32_e32 v1, s9
+; GFX9-NEXT: s_xor_b32 s0, s9, s8
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s10, s0, 1
+; GFX9-NEXT: s_sext_i32_i16 s3, s3
+; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2
+; GFX9-NEXT: v_trunc_f32_e32 v2, v2
+; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s10, 0
+; GFX9-NEXT: s_ashr_i32 s2, s2, 16
+; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s2
+; GFX9-NEXT: s_ashr_i32 s6, s6, 16
+; GFX9-NEXT: v_add_u32_e32 v1, s0, v2
+; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s6
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT: s_xor_b32 s0, s6, s2
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s8
+; GFX9-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: s_or_b32 s8, s0, 1
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s3
+; GFX9-NEXT: s_cselect_b32 s0, s8, 0
+; GFX9-NEXT: v_add_u32_e32 v0, s0, v3
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX9-NEXT: s_sext_i32_i16 s2, s7
+; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v2
+; GFX9-NEXT: s_xor_b32 s0, s2, s3
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s7, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX9-NEXT: v_trunc_f32_e32 v4, v4
+; GFX9-NEXT: v_mad_f32 v3, -v4, v2, v3
+; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v2|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s7, 0
+; GFX9-NEXT: v_add_u32_e32 v2, s0, v4
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, s3
+; GFX9-NEXT: v_sub_u32_e32 v1, s9, v1
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: v_sub_u32_e32 v0, s6, v0
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_sub_u32_e32 v2, s2, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-NEXT: global_store_short v3, v2, s[4:5] offset:4
+; GFX9-NEXT: global_store_dword v3, v0, s[4:5]
+; GFX9-NEXT: s_endpgm
%r = srem <3 x i16> %x, %y
store <3 x i16> %r, <3 x i16> addrspace(1)* %out
ret void
@@ -3268,63 +4602,119 @@ define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x
; CHECK-NEXT: store <3 x i15> [[TMP60]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_v3i15:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 30
-; GCN-NEXT: s_movk_i32 s3, 0x7fff
-; GCN-NEXT: s_and_b32 s9, s0, s3
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9
-; GCN-NEXT: v_mov_b32_e32 v2, s0
-; GCN-NEXT: s_and_b32 s8, s2, s3
-; GCN-NEXT: s_bfe_u32 s0, s0, 0xf000f
-; GCN-NEXT: v_cvt_f32_u32_e32 v5, s0
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s8
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v1
-; GCN-NEXT: s_bfe_u32 s2, s2, 0xf000f
-; GCN-NEXT: v_alignbit_b32 v2, s1, v2, 30
-; GCN-NEXT: v_cvt_f32_u32_e32 v6, s2
-; GCN-NEXT: v_mul_f32_e32 v4, v3, v4
-; GCN-NEXT: v_rcp_iflag_f32_e32 v7, v5
-; GCN-NEXT: v_and_b32_e32 v2, s3, v2
-; GCN-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-NEXT: v_mad_f32 v3, -v4, v1, v3
-; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1
-; GCN-NEXT: v_mul_f32_e32 v1, v6, v7
-; GCN-NEXT: v_and_b32_e32 v0, s3, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GCN-NEXT: v_mad_f32 v4, -v1, v5, v6
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v5
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; GCN-NEXT: v_mul_f32_e32 v1, v0, v6
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v5, v1
-; GCN-NEXT: v_mad_f32 v0, -v1, v2, v0
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v2
-; GCN-NEXT: v_and_b32_e32 v2, s3, v3
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GCN-NEXT: v_and_b32_e32 v3, s3, v4
-; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3
-; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
-; GCN-NEXT: v_or_b32_e32 v2, v2, v3
-; GCN-NEXT: v_or_b32_e32 v0, v2, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_waitcnt expcnt(0)
-; GCN-NEXT: v_and_b32_e32 v0, 0x1fff, v1
-; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_v3i15:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_alignbit_b32 v0, s3, v0, 30
+; GFX6-NEXT: s_movk_i32 s3, 0x7fff
+; GFX6-NEXT: s_and_b32 s9, s0, s3
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
+; GFX6-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-NEXT: s_and_b32 s8, s2, s3
+; GFX6-NEXT: s_bfe_u32 s0, s0, 0xf000f
+; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s0
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s8
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v1
+; GFX6-NEXT: s_bfe_u32 s2, s2, 0xf000f
+; GFX6-NEXT: v_alignbit_b32 v2, s1, v2, 30
+; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s2
+; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v5
+; GFX6-NEXT: v_and_b32_e32 v2, s3, v2
+; GFX6-NEXT: v_trunc_f32_e32 v4, v4
+; GFX6-NEXT: v_mad_f32 v3, -v4, v1, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, v6, v7
+; GFX6-NEXT: v_and_b32_e32 v0, s3, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; GFX6-NEXT: v_mad_f32 v4, -v1, v5, v6
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v2
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v5
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mul_f32_e32 v1, v0, v6
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v1
+; GFX6-NEXT: v_mad_f32 v0, -v1, v2, v0
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT: v_and_b32_e32 v2, s3, v3
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc
+; GFX6-NEXT: v_and_b32_e32 v3, s3, v4
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v3
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v0, 0x1fff, v1
+; GFX6-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_v3i15:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34
+; GFX9-NEXT: s_movk_i32 s8, 0x7fff
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s0, s4, s8
+; GFX9-NEXT: s_and_b32 s1, s6, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s1
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s0
+; GFX9-NEXT: s_bfe_u32 s0, s6, 0xf000f
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v1
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
+; GFX9-NEXT: s_bfe_u32 s1, s4, 0xf000f
+; GFX9-NEXT: v_alignbit_b32 v3, s7, v3, 30
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v6
+; GFX9-NEXT: v_and_b32_e32 v3, s8, v3
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_mad_f32 v4, -v5, v1, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v3
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v1
+; GFX9-NEXT: v_alignbit_b32 v0, s5, v0, 30
+; GFX9-NEXT: v_mul_f32_e32 v1, v7, v8
+; GFX9-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mad_f32 v5, -v1, v6, v7
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v3
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_f32_e32 v1, v0, v7
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v1
+; GFX9-NEXT: v_mad_f32 v0, -v1, v3, v0
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v3
+; GFX9-NEXT: v_and_b32_e32 v3, s8, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
+; GFX9-NEXT: v_and_b32_e32 v4, s8, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX9-NEXT: global_store_dword v2, v0, s[2:3]
+; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
+; GFX9-NEXT: global_store_short v2, v0, s[2:3] offset:4
+; GFX9-NEXT: s_endpgm
%r = udiv <3 x i15> %x, %y
store <3 x i15> %r, <3 x i15> addrspace(1)* %out
ret void
@@ -3401,71 +4791,135 @@ define amdgpu_kernel void @urem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x
; CHECK-NEXT: store <3 x i15> [[TMP66]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_v3i15:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 30
-; GCN-NEXT: s_movk_i32 s3, 0x7fff
-; GCN-NEXT: s_and_b32 s10, s0, s3
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s10
-; GCN-NEXT: s_and_b32 s9, s2, s3
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s9
-; GCN-NEXT: v_mov_b32_e32 v2, s0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v1
-; GCN-NEXT: v_alignbit_b32 v2, s1, v2, 30
-; GCN-NEXT: s_bfe_u32 s1, s0, 0xf000f
-; GCN-NEXT: v_cvt_f32_u32_e32 v5, s1
-; GCN-NEXT: v_mul_f32_e32 v4, v3, v4
-; GCN-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-NEXT: v_mad_f32 v3, -v4, v1, v3
-; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1
-; GCN-NEXT: s_bfe_u32 s10, s2, 0xf000f
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s10
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v5
-; GCN-NEXT: v_and_b32_e32 v2, s3, v2
-; GCN-NEXT: v_and_b32_e32 v0, s3, v0
-; GCN-NEXT: v_sub_i32_e32 v6, vcc, s2, v1
-; GCN-NEXT: v_mul_f32_e32 v1, v3, v4
-; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
-; GCN-NEXT: v_cvt_f32_u32_e32 v7, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mad_f32 v3, -v1, v5, v3
-; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v4
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_lshr_b32 s0, s0, 15
-; GCN-NEXT: v_mul_f32_e32 v3, v7, v8
-; GCN-NEXT: v_trunc_f32_e32 v3, v3
-; GCN-NEXT: v_cvt_u32_f32_e32 v5, v3
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mad_f32 v3, -v3, v4, v7
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s0
-; GCN-NEXT: v_mul_lo_u32 v2, v3, v2
-; GCN-NEXT: s_lshr_b32 s8, s2, 15
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s8, v1
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0
-; GCN-NEXT: v_and_b32_e32 v3, s3, v3
-; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
-; GCN-NEXT: v_and_b32_e32 v2, s3, v6
-; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3
-; GCN-NEXT: v_or_b32_e32 v2, v2, v3
-; GCN-NEXT: v_or_b32_e32 v0, v2, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_waitcnt expcnt(0)
-; GCN-NEXT: v_and_b32_e32 v0, 0x1fff, v1
-; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_v3i15:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_alignbit_b32 v0, s3, v0, 30
+; GFX6-NEXT: s_movk_i32 s3, 0x7fff
+; GFX6-NEXT: s_and_b32 s10, s0, s3
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s10
+; GFX6-NEXT: s_and_b32 s9, s2, s3
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s9
+; GFX6-NEXT: v_mov_b32_e32 v2, s0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v1
+; GFX6-NEXT: v_alignbit_b32 v2, s1, v2, 30
+; GFX6-NEXT: s_bfe_u32 s1, s0, 0xf000f
+; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s1
+; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX6-NEXT: v_trunc_f32_e32 v4, v4
+; GFX6-NEXT: v_mad_f32 v3, -v4, v1, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1
+; GFX6-NEXT: s_bfe_u32 s10, s2, 0xf000f
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s10
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v5
+; GFX6-NEXT: v_and_b32_e32 v2, s3, v2
+; GFX6-NEXT: v_and_b32_e32 v0, s3, v0
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s2, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, v3, v4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v4, v2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v7, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mad_f32 v3, -v1, v5, v3
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v4
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_lshr_b32 s0, s0, 15
+; GFX6-NEXT: v_mul_f32_e32 v3, v7, v8
+; GFX6-NEXT: v_trunc_f32_e32 v3, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v3
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mad_f32 v3, -v3, v4, v7
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s0
+; GFX6-NEXT: v_mul_lo_u32 v2, v3, v2
+; GFX6-NEXT: s_lshr_b32 s8, s2, 15
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s8, v1
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: v_and_b32_e32 v3, s3, v3
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
+; GFX6-NEXT: v_and_b32_e32 v2, s3, v6
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v3
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v0, 0x1fff, v1
+; GFX6-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_v3i15:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34
+; GFX9-NEXT: s_movk_i32 s8, 0x7fff
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_alignbit_b32 v0, s5, v0, 30
+; GFX9-NEXT: s_and_b32 s5, s6, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5
+; GFX9-NEXT: s_and_b32 s0, s4, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s0
+; GFX9-NEXT: s_bfe_u32 s5, s6, 0xf000f
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v1
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s5
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
+; GFX9-NEXT: v_alignbit_b32 v3, s7, v3, 30
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_mad_f32 v4, -v5, v1, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v1
+; GFX9-NEXT: s_bfe_u32 s1, s4, 0xf000f
+; GFX9-NEXT: v_and_b32_e32 v3, s8, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v6
+; GFX9-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v9, v5
+; GFX9-NEXT: s_lshr_b32 s0, s6, 15
+; GFX9-NEXT: v_mul_f32_e32 v4, v7, v8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v0
+; GFX9-NEXT: v_trunc_f32_e32 v4, v4
+; GFX9-NEXT: v_mad_f32 v7, -v4, v6, v7
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v7|, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_mul_f32_e32 v6, v8, v9
+; GFX9-NEXT: v_trunc_f32_e32 v6, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mad_f32 v6, -v6, v5, v8
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, v5
+; GFX9-NEXT: v_mul_lo_u32 v4, v4, s0
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v5, v3
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s6
+; GFX9-NEXT: s_lshr_b32 s0, s4, 15
+; GFX9-NEXT: v_sub_u32_e32 v4, s0, v4
+; GFX9-NEXT: v_and_b32_e32 v4, s8, v4
+; GFX9-NEXT: v_sub_u32_e32 v5, s4, v1
+; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
+; GFX9-NEXT: v_and_b32_e32 v3, s8, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX9-NEXT: global_store_dword v2, v0, s[2:3]
+; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
+; GFX9-NEXT: global_store_short v2, v0, s[2:3] offset:4
+; GFX9-NEXT: s_endpgm
%r = urem <3 x i15> %x, %y
store <3 x i15> %r, <3 x i15> addrspace(1)* %out
ret void
@@ -3548,77 +5002,147 @@ define amdgpu_kernel void @sdiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x
; CHECK-NEXT: store <3 x i15> [[TMP72]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_v3i15:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 30
-; GCN-NEXT: s_bfe_i32 s3, s0, 0xf0000
-; GCN-NEXT: v_cvt_f32_i32_e32 v2, s3
-; GCN-NEXT: v_mov_b32_e32 v1, s0
-; GCN-NEXT: v_alignbit_b32 v1, s1, v1, 30
-; GCN-NEXT: s_bfe_i32 s1, s2, 0xf0000
-; GCN-NEXT: v_cvt_f32_i32_e32 v3, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
-; GCN-NEXT: s_xor_b32 s1, s1, s3
-; GCN-NEXT: s_bfe_i32 s0, s0, 0xf000f
-; GCN-NEXT: s_ashr_i32 s1, s1, 30
-; GCN-NEXT: v_mul_f32_e32 v4, v3, v4
-; GCN-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
-; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4
-; GCN-NEXT: v_cvt_f32_i32_e32 v3, s0
-; GCN-NEXT: s_or_b32 s1, s1, 1
-; GCN-NEXT: v_mov_b32_e32 v5, s1
-; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
-; GCN-NEXT: s_bfe_i32 s1, s2, 0xf000f
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT: v_cvt_f32_i32_e32 v4, s1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3
-; GCN-NEXT: s_xor_b32 s0, s1, s0
-; GCN-NEXT: v_bfe_i32 v1, v1, 0, 15
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: v_mul_f32_e32 v5, v4, v5
-; GCN-NEXT: v_trunc_f32_e32 v5, v5
-; GCN-NEXT: v_mad_f32 v4, -v5, v3, v4
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v3|
-; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5
-; GCN-NEXT: v_cvt_f32_i32_e32 v4, v1
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mov_b32_e32 v6, s0
-; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
-; GCN-NEXT: v_bfe_i32 v0, v0, 0, 15
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT: v_cvt_f32_i32_e32 v5, v0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4
-; GCN-NEXT: v_xor_b32_e32 v0, v0, v1
-; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0
-; GCN-NEXT: v_or_b32_e32 v0, 1, v0
-; GCN-NEXT: v_mul_f32_e32 v1, v5, v6
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mad_f32 v5, -v1, v4, v5
-; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, |v4|
-; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-NEXT: s_movk_i32 s0, 0x7fff
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_and_b32_e32 v3, s0, v3
-; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
-; GCN-NEXT: v_and_b32_e32 v2, s0, v2
-; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3
-; GCN-NEXT: v_or_b32_e32 v2, v2, v3
-; GCN-NEXT: v_or_b32_e32 v0, v2, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_waitcnt expcnt(0)
-; GCN-NEXT: v_and_b32_e32 v0, 0x1fff, v1
-; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_v3i15:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_alignbit_b32 v0, s3, v0, 30
+; GFX6-NEXT: s_bfe_i32 s3, s0, 0xf0000
+; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s3
+; GFX6-NEXT: v_mov_b32_e32 v1, s0
+; GFX6-NEXT: v_alignbit_b32 v1, s1, v1, 30
+; GFX6-NEXT: s_bfe_i32 s1, s2, 0xf0000
+; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v2
+; GFX6-NEXT: s_xor_b32 s1, s1, s3
+; GFX6-NEXT: s_bfe_i32 s0, s0, 0xf000f
+; GFX6-NEXT: s_ashr_i32 s1, s1, 30
+; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX6-NEXT: v_trunc_f32_e32 v4, v4
+; GFX6-NEXT: v_mad_f32 v3, -v4, v2, v3
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
+; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s0
+; GFX6-NEXT: s_or_b32 s1, s1, 1
+; GFX6-NEXT: v_mov_b32_e32 v5, s1
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
+; GFX6-NEXT: s_bfe_i32 s1, s2, 0xf000f
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3
+; GFX6-NEXT: s_xor_b32 s0, s1, s0
+; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 15
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v5
+; GFX6-NEXT: v_mad_f32 v4, -v5, v3, v4
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v3|
+; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX6-NEXT: v_cvt_f32_i32_e32 v4, v1
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mov_b32_e32 v6, s0
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 15
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: v_cvt_f32_i32_e32 v5, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v4
+; GFX6-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX6-NEXT: v_ashrrev_i32_e32 v0, 30, v0
+; GFX6-NEXT: v_or_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, v5, v6
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mad_f32 v5, -v1, v4, v5
+; GFX6-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, |v4|
+; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX6-NEXT: s_movk_i32 s0, 0x7fff
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_and_b32_e32 v3, s0, v3
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
+; GFX6-NEXT: v_and_b32_e32 v2, s0, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v3
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v0, 0x1fff, v1
+; GFX6-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_v3i15:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_bfe_i32 s1, s4, 0xf0000
+; GFX9-NEXT: s_bfe_i32 s0, s6, 0xf0000
+; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s0
+; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s1
+; GFX9-NEXT: s_xor_b32 s0, s1, s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v3
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: v_alignbit_b32 v0, s5, v0, 30
+; GFX9-NEXT: s_or_b32 s5, s0, 1
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_mad_f32 v4, -v5, v3, v4
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s5, 0
+; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX9-NEXT: s_bfe_i32 s1, s6, 0xf000f
+; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s1
+; GFX9-NEXT: v_mov_b32_e32 v1, s6
+; GFX9-NEXT: v_add_u32_e32 v4, s0, v5
+; GFX9-NEXT: s_bfe_i32 s0, s4, 0xf000f
+; GFX9-NEXT: v_cvt_f32_i32_e32 v5, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v3
+; GFX9-NEXT: v_alignbit_b32 v1, s7, v1, 30
+; GFX9-NEXT: s_xor_b32 s0, s0, s1
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: v_mul_f32_e32 v6, v5, v6
+; GFX9-NEXT: v_trunc_f32_e32 v6, v6
+; GFX9-NEXT: v_mad_f32 v5, -v6, v3, v5
+; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 15
+; GFX9-NEXT: s_or_b32 s4, s0, 1
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, |v3|
+; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v1
+; GFX9-NEXT: v_cvt_i32_f32_e32 v6, v6
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s4, 0
+; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 15
+; GFX9-NEXT: v_add_u32_e32 v5, s0, v6
+; GFX9-NEXT: v_cvt_f32_i32_e32 v6, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v3
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0
+; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, v6, v7
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_i32_f32_e32 v7, v1
+; GFX9-NEXT: v_mad_f32 v1, -v1, v3, v6
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3|
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX9-NEXT: s_movk_i32 s0, 0x7fff
+; GFX9-NEXT: v_add_u32_e32 v0, v7, v0
+; GFX9-NEXT: v_and_b32_e32 v3, s0, v4
+; GFX9-NEXT: v_and_b32_e32 v4, s0, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX9-NEXT: global_store_dword v2, v0, s[2:3]
+; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
+; GFX9-NEXT: global_store_short v2, v0, s[2:3] offset:4
+; GFX9-NEXT: s_endpgm
%r = sdiv <3 x i15> %x, %y
store <3 x i15> %r, <3 x i15> addrspace(1)* %out
ret void
@@ -3707,91 +5231,175 @@ define amdgpu_kernel void @srem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x
; CHECK-NEXT: store <3 x i15> [[TMP78]], <3 x i15> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_v3i15:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 30
-; GCN-NEXT: s_movk_i32 s3, 0x7fff
-; GCN-NEXT: s_and_b32 s11, s0, s3
-; GCN-NEXT: s_bfe_i32 s11, s11, 0xf0000
-; GCN-NEXT: v_cvt_f32_i32_e32 v2, s11
-; GCN-NEXT: s_and_b32 s9, s2, s3
-; GCN-NEXT: s_bfe_i32 s9, s9, 0xf0000
-; GCN-NEXT: v_cvt_f32_i32_e32 v3, s9
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
-; GCN-NEXT: s_xor_b32 s9, s9, s11
-; GCN-NEXT: s_ashr_i32 s9, s9, 30
-; GCN-NEXT: s_or_b32 s9, s9, 1
-; GCN-NEXT: v_mul_f32_e32 v4, v3, v4
-; GCN-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3
-; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4
-; GCN-NEXT: v_mov_b32_e32 v5, s9
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
-; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
-; GCN-NEXT: v_mov_b32_e32 v1, s0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT: s_bfe_u32 s12, s0, 0xf000f
-; GCN-NEXT: v_alignbit_b32 v1, s1, v1, 30
-; GCN-NEXT: v_mul_lo_u32 v2, v2, s0
-; GCN-NEXT: s_lshr_b32 s1, s0, 15
-; GCN-NEXT: s_bfe_i32 s0, s12, 0xf0000
-; GCN-NEXT: v_cvt_f32_i32_e32 v3, s0
-; GCN-NEXT: s_bfe_u32 s10, s2, 0xf000f
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
-; GCN-NEXT: s_lshr_b32 s8, s2, 15
-; GCN-NEXT: s_bfe_i32 s2, s10, 0xf0000
-; GCN-NEXT: v_cvt_f32_i32_e32 v4, s2
-; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3
-; GCN-NEXT: s_xor_b32 s0, s2, s0
-; GCN-NEXT: s_ashr_i32 s0, s0, 30
-; GCN-NEXT: s_or_b32 s0, s0, 1
-; GCN-NEXT: v_mul_f32_e32 v5, v4, v5
-; GCN-NEXT: v_trunc_f32_e32 v5, v5
-; GCN-NEXT: v_mad_f32 v4, -v5, v3, v4
-; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5
-; GCN-NEXT: v_and_b32_e32 v1, s3, v1
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v3|
-; GCN-NEXT: v_mov_b32_e32 v6, s0
-; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
-; GCN-NEXT: v_bfe_i32 v4, v1, 0, 15
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT: v_cvt_f32_i32_e32 v5, v4
-; GCN-NEXT: v_and_b32_e32 v0, s3, v0
-; GCN-NEXT: v_bfe_i32 v6, v0, 0, 15
-; GCN-NEXT: v_cvt_f32_i32_e32 v7, v6
-; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v5
-; GCN-NEXT: v_xor_b32_e32 v4, v6, v4
-; GCN-NEXT: v_ashrrev_i32_e32 v4, 30, v4
-; GCN-NEXT: v_or_b32_e32 v4, 1, v4
-; GCN-NEXT: v_mul_f32_e32 v6, v7, v8
-; GCN-NEXT: v_trunc_f32_e32 v6, v6
-; GCN-NEXT: v_mad_f32 v7, -v6, v5, v7
-; GCN-NEXT: v_cvt_i32_f32_e32 v6, v6
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v7|, |v5|
-; GCN-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v3, v3, s1
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT: v_mul_lo_u32 v1, v4, v1
-; GCN-NEXT: v_and_b32_e32 v2, s3, v2
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s8, v3
-; GCN-NEXT: v_and_b32_e32 v3, s3, v3
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3
-; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
-; GCN-NEXT: v_or_b32_e32 v2, v2, v3
-; GCN-NEXT: v_or_b32_e32 v0, v2, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_waitcnt expcnt(0)
-; GCN-NEXT: v_and_b32_e32 v0, 0x1fff, v1
-; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_v3i15:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_alignbit_b32 v0, s3, v0, 30
+; GFX6-NEXT: s_movk_i32 s3, 0x7fff
+; GFX6-NEXT: s_and_b32 s11, s0, s3
+; GFX6-NEXT: s_bfe_i32 s11, s11, 0xf0000
+; GFX6-NEXT: v_cvt_f32_i32_e32 v2, s11
+; GFX6-NEXT: s_and_b32 s9, s2, s3
+; GFX6-NEXT: s_bfe_i32 s9, s9, 0xf0000
+; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s9
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v2
+; GFX6-NEXT: s_xor_b32 s9, s9, s11
+; GFX6-NEXT: s_ashr_i32 s9, s9, 30
+; GFX6-NEXT: s_or_b32 s9, s9, 1
+; GFX6-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX6-NEXT: v_trunc_f32_e32 v4, v4
+; GFX6-NEXT: v_mad_f32 v3, -v4, v2, v3
+; GFX6-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX6-NEXT: v_mov_b32_e32 v5, s9
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
+; GFX6-NEXT: v_mov_b32_e32 v1, s0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT: s_bfe_u32 s12, s0, 0xf000f
+; GFX6-NEXT: v_alignbit_b32 v1, s1, v1, 30
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, s0
+; GFX6-NEXT: s_lshr_b32 s1, s0, 15
+; GFX6-NEXT: s_bfe_i32 s0, s12, 0xf0000
+; GFX6-NEXT: v_cvt_f32_i32_e32 v3, s0
+; GFX6-NEXT: s_bfe_u32 s10, s2, 0xf000f
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT: s_lshr_b32 s8, s2, 15
+; GFX6-NEXT: s_bfe_i32 s2, s10, 0xf0000
+; GFX6-NEXT: v_cvt_f32_i32_e32 v4, s2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v5, v3
+; GFX6-NEXT: s_xor_b32 s0, s2, s0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 30
+; GFX6-NEXT: s_or_b32 s0, s0, 1
+; GFX6-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX6-NEXT: v_trunc_f32_e32 v5, v5
+; GFX6-NEXT: v_mad_f32 v4, -v5, v3, v4
+; GFX6-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX6-NEXT: v_and_b32_e32 v1, s3, v1
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v3|
+; GFX6-NEXT: v_mov_b32_e32 v6, s0
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc
+; GFX6-NEXT: v_bfe_i32 v4, v1, 0, 15
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: v_cvt_f32_i32_e32 v5, v4
+; GFX6-NEXT: v_and_b32_e32 v0, s3, v0
+; GFX6-NEXT: v_bfe_i32 v6, v0, 0, 15
+; GFX6-NEXT: v_cvt_f32_i32_e32 v7, v6
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v5
+; GFX6-NEXT: v_xor_b32_e32 v4, v6, v4
+; GFX6-NEXT: v_ashrrev_i32_e32 v4, 30, v4
+; GFX6-NEXT: v_or_b32_e32 v4, 1, v4
+; GFX6-NEXT: v_mul_f32_e32 v6, v7, v8
+; GFX6-NEXT: v_trunc_f32_e32 v6, v6
+; GFX6-NEXT: v_mad_f32 v7, -v6, v5, v7
+; GFX6-NEXT: v_cvt_i32_f32_e32 v6, v6
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v7|, |v5|
+; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, s1
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GFX6-NEXT: v_mul_lo_u32 v1, v4, v1
+; GFX6-NEXT: v_and_b32_e32 v2, s3, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s8, v3
+; GFX6-NEXT: v_and_b32_e32 v3, s3, v3
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 15, v3
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 30
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v0, 0x1fff, v1
+; GFX6-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_v3i15:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34
+; GFX9-NEXT: s_movk_i32 s8, 0x7fff
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s0, s4, s8
+; GFX9-NEXT: s_and_b32 s1, s6, s8
+; GFX9-NEXT: s_bfe_i32 s1, s1, 0xf0000
+; GFX9-NEXT: v_cvt_f32_i32_e32 v2, s1
+; GFX9-NEXT: s_bfe_i32 s0, s0, 0xf0000
+; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s0
+; GFX9-NEXT: s_xor_b32 s0, s0, s1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v2
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s6
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX9-NEXT: v_trunc_f32_e32 v4, v4
+; GFX9-NEXT: v_mad_f32 v3, -v4, v2, v3
+; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX9-NEXT: v_alignbit_b32 v0, s5, v0, 30
+; GFX9-NEXT: v_alignbit_b32 v1, s7, v1, 30
+; GFX9-NEXT: s_or_b32 s11, s0, 1
+; GFX9-NEXT: s_lshr_b32 s9, s4, 15
+; GFX9-NEXT: s_bfe_u32 s5, s4, 0xf000f
+; GFX9-NEXT: s_lshr_b32 s7, s6, 15
+; GFX9-NEXT: s_bfe_u32 s10, s6, 0xf000f
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v2|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s11, 0
+; GFX9-NEXT: v_add_u32_e32 v2, s0, v4
+; GFX9-NEXT: s_bfe_i32 s0, s10, 0xf0000
+; GFX9-NEXT: v_cvt_f32_i32_e32 v3, s0
+; GFX9-NEXT: s_bfe_i32 s1, s5, 0xf0000
+; GFX9-NEXT: v_cvt_f32_i32_e32 v4, s1
+; GFX9-NEXT: s_xor_b32 s0, s1, s0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v3
+; GFX9-NEXT: s_ashr_i32 s0, s0, 30
+; GFX9-NEXT: s_or_b32 s5, s0, 1
+; GFX9-NEXT: v_and_b32_e32 v1, s8, v1
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_mad_f32 v4, -v5, v3, v4
+; GFX9-NEXT: v_cvt_i32_f32_e32 v5, v5
+; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v3|
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s5, 0
+; GFX9-NEXT: v_bfe_i32 v4, v1, 0, 15
+; GFX9-NEXT: v_add_u32_e32 v3, s0, v5
+; GFX9-NEXT: v_cvt_f32_i32_e32 v5, v4
+; GFX9-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX9-NEXT: v_bfe_i32 v6, v0, 0, 15
+; GFX9-NEXT: v_cvt_f32_i32_e32 v7, v6
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v5
+; GFX9-NEXT: v_xor_b32_e32 v4, v6, v4
+; GFX9-NEXT: v_ashrrev_i32_e32 v4, 30, v4
+; GFX9-NEXT: v_or_b32_e32 v4, 1, v4
+; GFX9-NEXT: v_mul_f32_e32 v6, v7, v8
+; GFX9-NEXT: v_trunc_f32_e32 v6, v6
+; GFX9-NEXT: v_cvt_i32_f32_e32 v8, v6
+; GFX9-NEXT: v_mad_f32 v6, -v6, v5, v7
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, |v5|
+; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v3, s7
+; GFX9-NEXT: v_add_u32_e32 v4, v8, v4
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, s6
+; GFX9-NEXT: v_mul_lo_u32 v1, v4, v1
+; GFX9-NEXT: v_sub_u32_e32 v3, s9, v3
+; GFX9-NEXT: v_and_b32_e32 v3, s8, v3
+; GFX9-NEXT: v_sub_u32_e32 v2, s4, v2
+; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
+; GFX9-NEXT: v_and_b32_e32 v2, s8, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 15, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX9-NEXT: global_store_dword v4, v0, s[2:3]
+; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
+; GFX9-NEXT: global_store_short v4, v0, s[2:3] offset:4
+; GFX9-NEXT: s_endpgm
%r = srem <3 x i15> %x, %y
store <3 x i15> %r, <3 x i15> addrspace(1)* %out
ret void
@@ -3803,21 +5411,36 @@ define amdgpu_kernel void @udiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_i32_oddk_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: v_mov_b32_e32 v0, 0xb2a50881
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mul_hi_u32 v0, s0, v0
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s0, v0
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_lshrrev_b32_e32 v0, 20, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_i32_oddk_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: v_mov_b32_e32 v0, 0xb2a50881
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 20, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_i32_oddk_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_mul_hi_u32 s0, s4, 0xb2a50881
+; GFX9-NEXT: s_sub_i32 s1, s4, s0
+; GFX9-NEXT: s_lshr_b32 s1, s1, 1
+; GFX9-NEXT: s_add_i32 s1, s1, s0
+; GFX9-NEXT: s_lshr_b32 s0, s1, 20
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = udiv i32 %x, 1235195
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -3829,17 +5452,28 @@ define amdgpu_kernel void @udiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x)
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_i32_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b32 s0, s0, 12
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_i32_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshr_b32 s0, s0, 12
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_i32_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshr_b32 s0, s4, 12
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = udiv i32 %x, 4096
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -3852,18 +5486,30 @@ define amdgpu_kernel void @udiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_i32_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_add_i32 s1, s1, 12
-; GCN-NEXT: s_lshr_b32 s0, s0, s1
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_i32_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_add_i32 s1, s1, 12
+; GFX6-NEXT: s_lshr_b32 s0, s0, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_i32_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_add_i32 s0, s5, 12
+; GFX9-NEXT: s_lshr_b32 s0, s4, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX9-NEXT: s_endpgm
%shl.y = shl i32 4096, %y
%r = udiv i32 %x, %shl.y
store i32 %r, i32 addrspace(1)* %out
@@ -3881,19 +5527,32 @@ define amdgpu_kernel void @udiv_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out,
; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_v2i32_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b32 s0, s0, 12
-; GCN-NEXT: s_lshr_b32 s1, s1, 12
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_v2i32_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshr_b32 s0, s0, 12
+; GFX6-NEXT: s_lshr_b32 s1, s1, 12
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_v2i32_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshr_b32 s0, s4, 12
+; GFX9-NEXT: s_lshr_b32 s1, s5, 12
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = udiv <2 x i32> %x, <i32 4096, i32 4096>
store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void
@@ -3910,23 +5569,40 @@ define amdgpu_kernel void @udiv_v2i32_mixed_pow2k_denom(<2 x i32> addrspace(1)*
; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_v2i32_mixed_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GCN-NEXT: v_mov_b32_e32 v0, 0x100101
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
-; GCN-NEXT: s_lshr_b32 s0, s0, 12
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s1, v0
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 11, v0
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_v2i32_mixed_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x100101
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT: s_lshr_b32 s0, s0, 12
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 11, v0
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_v2i32_mixed_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_mul_hi_u32 s1, s5, 0x100101
+; GFX9-NEXT: s_lshr_b32 s0, s4, 12
+; GFX9-NEXT: s_sub_i32 s4, s5, s1
+; GFX9-NEXT: s_lshr_b32 s4, s4, 1
+; GFX9-NEXT: s_add_i32 s4, s4, s1
+; GFX9-NEXT: s_lshr_b32 s1, s4, 11
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = udiv <2 x i32> %x, <i32 4096, i32 4095>
store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void
@@ -4002,59 +5678,112 @@ define amdgpu_kernel void @udiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %ou
; CHECK-NEXT: store <2 x i32> [[TMP64]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_v2i32_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
-; GCN-NEXT: s_movk_i32 s4, 0x1000
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b32 s8, s4, s2
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
-; GCN-NEXT: s_lshl_b32 s9, s4, s3
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: s_mov_b32 s0, 0x4f7ffffe
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GCN-NEXT: v_mul_f32_e32 v0, s0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s0, v1
-; GCN-NEXT: s_sub_i32 s0, 0, s8
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mul_lo_u32 v2, s0, v0
-; GCN-NEXT: s_sub_i32 s0, 0, s9
-; GCN-NEXT: v_mul_lo_u32 v3, s0, v1
-; GCN-NEXT: v_mul_hi_u32 v2, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mul_hi_u32 v0, s2, v0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; GCN-NEXT: v_mul_hi_u32 v1, s3, v1
-; GCN-NEXT: v_mul_lo_u32 v2, v0, s8
-; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v0
-; GCN-NEXT: v_mul_lo_u32 v4, v1, s9
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s8, v2
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s3, v4
-; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v1
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v2
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s9, v2
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v2
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_v2i32_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
+; GFX6-NEXT: s_movk_i32 s4, 0x1000
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b32 s8, s4, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GFX6-NEXT: s_lshl_b32 s9, s4, s3
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s0, 0x4f7ffffe
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_f32_e32 v0, s0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, s0, v1
+; GFX6-NEXT: s_sub_i32 s0, 0, s8
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, s0, v0
+; GFX6-NEXT: s_sub_i32 s0, 0, s9
+; GFX6-NEXT: v_mul_lo_u32 v3, s0, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
+; GFX6-NEXT: v_mul_hi_u32 v1, s3, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s8
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, v1, s9
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s3, v4
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_v2i32_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
+; GFX9-NEXT: s_movk_i32 s4, 0x1000
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b32 s7, s4, s2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
+; GFX9-NEXT: s_lshl_b32 s6, s4, s3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s6
+; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: s_sub_i32 s3, 0, s6
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_sub_i32 s2, 0, s7
+; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v1, s3, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, s7
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, s6
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
+; GFX9-NEXT: v_sub_u32_e32 v3, s2, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s7, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_sub_u32_e32 v4, s3, v4
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v4
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX9-NEXT: v_subrev_u32_e32 v3, s6, v4
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = udiv <2 x i32> %x, %shl.y
store <2 x i32> %r, <2 x i32> addrspace(1)* %out
@@ -4067,23 +5796,40 @@ define amdgpu_kernel void @urem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_i32_oddk_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: v_mov_b32_e32 v0, 0xb2a50881
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mul_hi_u32 v0, s0, v0
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s0, v0
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_lshrrev_b32_e32 v0, 20, v0
-; GCN-NEXT: v_mul_u32_u24_e32 v0, 0x12d8fb, v0
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_i32_oddk_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: v_mov_b32_e32 v0, 0xb2a50881
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 20, v0
+; GFX6-NEXT: v_mul_u32_u24_e32 v0, 0x12d8fb, v0
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_i32_oddk_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x12d8fb
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_mul_hi_u32 s0, s4, 0xb2a50881
+; GFX9-NEXT: s_sub_i32 s1, s4, s0
+; GFX9-NEXT: s_lshr_b32 s1, s1, 1
+; GFX9-NEXT: s_add_i32 s1, s1, s0
+; GFX9-NEXT: s_lshr_b32 s0, s1, 20
+; GFX9-NEXT: v_mul_u32_u24_e32 v1, s0, v1
+; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1
+; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = urem i32 %x, 1235195
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -4095,17 +5841,28 @@ define amdgpu_kernel void @urem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x)
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_i32_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_and_b32 s0, s0, 0xfff
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_i32_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s0, s0, 0xfff
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_i32_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s0, s4, 0xfff
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = urem i32 %x, 4096
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -4118,19 +5875,32 @@ define amdgpu_kernel void @urem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_i32_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b32 s1, 0x1000, s1
-; GCN-NEXT: s_add_i32 s1, s1, -1
-; GCN-NEXT: s_and_b32 s0, s0, s1
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_i32_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b32 s1, 0x1000, s1
+; GFX6-NEXT: s_add_i32 s1, s1, -1
+; GFX6-NEXT: s_and_b32 s0, s0, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_i32_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b32 s0, 0x1000, s5
+; GFX9-NEXT: s_add_i32 s0, s0, -1
+; GFX9-NEXT: s_and_b32 s0, s4, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX9-NEXT: s_endpgm
%shl.y = shl i32 4096, %y
%r = urem i32 %x, %shl.y
store i32 %r, i32 addrspace(1)* %out
@@ -4148,20 +5918,34 @@ define amdgpu_kernel void @urem_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out,
; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_v2i32_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GCN-NEXT: s_movk_i32 s2, 0xfff
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_and_b32 s0, s0, s2
-; GCN-NEXT: s_and_b32 s1, s1, s2
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_v2i32_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT: s_movk_i32 s2, 0xfff
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s0, s0, s2
+; GFX6-NEXT: s_and_b32 s1, s1, s2
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_v2i32_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: s_movk_i32 s0, 0xfff
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s1, s4, s0
+; GFX9-NEXT: s_and_b32 s0, s5, s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = urem <2 x i32> %x, <i32 4096, i32 4096>
store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void
@@ -4233,55 +6017,104 @@ define amdgpu_kernel void @urem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %ou
; CHECK-NEXT: store <2 x i32> [[TMP60]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_v2i32_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
-; GCN-NEXT: s_movk_i32 s4, 0x1000
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b32 s8, s4, s2
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
-; GCN-NEXT: s_lshl_b32 s3, s4, s3
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3
-; GCN-NEXT: s_mov_b32 s4, 0x4f7ffffe
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: s_sub_i32 s2, 0, s8
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GCN-NEXT: v_mul_f32_e32 v0, s4, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GCN-NEXT: v_mul_lo_u32 v2, s2, v0
-; GCN-NEXT: s_sub_i32 s2, 0, s3
-; GCN-NEXT: v_mul_lo_u32 v3, s2, v1
-; GCN-NEXT: v_mul_hi_u32 v2, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mul_hi_u32 v0, s0, v0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; GCN-NEXT: v_mul_hi_u32 v1, s1, v1
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s8
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s3
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_v2i32_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
+; GFX6-NEXT: s_movk_i32 s4, 0x1000
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b32 s8, s4, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GFX6-NEXT: s_lshl_b32 s3, s4, s3
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3
+; GFX6-NEXT: s_mov_b32 s4, 0x4f7ffffe
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: s_sub_i32 s2, 0, s8
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_f32_e32 v0, s4, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, s4, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
+; GFX6-NEXT: s_sub_i32 s2, 0, s3
+; GFX6-NEXT: v_mul_lo_u32 v3, s2, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
+; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s8
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_v2i32_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
+; GFX9-NEXT: s_movk_i32 s4, 0x1000
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b32 s5, s4, s3
+; GFX9-NEXT: s_lshl_b32 s4, s4, s2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5
+; GFX9-NEXT: s_mov_b32 s2, 0x4f7ffffe
+; GFX9-NEXT: s_sub_i32 s3, 0, s5
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_sub_i32 s2, 0, s4
+; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v1, s3, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s4
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s5
+; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_sub_u32_e32 v1, s3, v1
+; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s5, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = urem <2 x i32> %x, %shl.y
store <2 x i32> %r, <2 x i32> addrspace(1)* %out
@@ -4294,21 +6127,36 @@ define amdgpu_kernel void @sdiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_i32_oddk_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: v_mov_b32_e32 v0, 0xd9528441
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mul_hi_i32 v0, s0, v0
-; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v0
-; GCN-NEXT: v_ashrrev_i32_e32 v0, 20, v0
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_i32_oddk_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: v_mov_b32_e32 v0, 0xd9528441
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mul_hi_i32 v0, s0, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 31, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v0, 20, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_i32_oddk_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_mul_hi_i32 s0, s4, 0xd9528441
+; GFX9-NEXT: s_add_i32 s0, s0, s4
+; GFX9-NEXT: s_lshr_b32 s1, s0, 31
+; GFX9-NEXT: s_ashr_i32 s0, s0, 20
+; GFX9-NEXT: s_add_i32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = sdiv i32 %x, 1235195
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -4320,20 +6168,34 @@ define amdgpu_kernel void @sdiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x)
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_i32_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: s_lshr_b32 s1, s1, 20
-; GCN-NEXT: s_add_i32 s0, s0, s1
-; GCN-NEXT: s_ashr_i32 s0, s0, 12
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_i32_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s1, s0, 31
+; GFX6-NEXT: s_lshr_b32 s1, s1, 20
+; GFX6-NEXT: s_add_i32 s0, s0, s1
+; GFX6-NEXT: s_ashr_i32 s0, s0, 12
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_i32_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s0, s4, 31
+; GFX9-NEXT: s_lshr_b32 s0, s0, 20
+; GFX9-NEXT: s_add_i32 s4, s4, s0
+; GFX9-NEXT: s_ashr_i32 s0, s4, 12
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = sdiv i32 %x, 4096
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -4346,44 +6208,82 @@ define amdgpu_kernel void @sdiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_i32_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b32 s3, 0x1000, s3
-; GCN-NEXT: s_ashr_i32 s4, s3, 31
-; GCN-NEXT: s_add_i32 s3, s3, s4
-; GCN-NEXT: s_xor_b32 s7, s3, s4
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s7
-; GCN-NEXT: s_sub_i32 s3, 0, s7
-; GCN-NEXT: s_ashr_i32 s5, s2, 31
-; GCN-NEXT: s_add_i32 s2, s2, s5
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: s_xor_b32 s6, s2, s5
-; GCN-NEXT: s_xor_b32 s4, s5, s4
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_lo_u32 v1, s3, v0
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s6, v0
-; GCN-NEXT: v_mul_lo_u32 v1, v0, s7
-; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s6, v1
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s7, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: v_xor_b32_e32 v0, s4, v0
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_i32_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s3
+; GFX6-NEXT: s_ashr_i32 s4, s3, 31
+; GFX6-NEXT: s_add_i32 s3, s3, s4
+; GFX6-NEXT: s_xor_b32 s7, s3, s4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s7
+; GFX6-NEXT: s_sub_i32 s3, 0, s7
+; GFX6-NEXT: s_ashr_i32 s5, s2, 31
+; GFX6-NEXT: s_add_i32 s2, s2, s5
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: s_xor_b32 s6, s2, s5
+; GFX6-NEXT: s_xor_b32 s4, s5, s4
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s6, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, v0, s7
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s6, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s7, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_i32_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s3
+; GFX9-NEXT: s_ashr_i32 s4, s3, 31
+; GFX9-NEXT: s_add_i32 s3, s3, s4
+; GFX9-NEXT: s_xor_b32 s5, s3, s4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s5
+; GFX9-NEXT: s_sub_i32 s3, 0, s5
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX9-NEXT: s_ashr_i32 s3, s2, 31
+; GFX9-NEXT: s_add_i32 s2, s2, s3
+; GFX9-NEXT: s_xor_b32 s2, s2, s3
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v0, s5
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX9-NEXT: s_xor_b32 s2, s3, s4
+; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0
+; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%shl.y = shl i32 4096, %y
%r = sdiv i32 %x, %shl.y
store i32 %r, i32 addrspace(1)* %out
@@ -4401,25 +6301,44 @@ define amdgpu_kernel void @sdiv_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out,
; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_v2i32_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s2, s0, 31
-; GCN-NEXT: s_lshr_b32 s2, s2, 20
-; GCN-NEXT: s_ashr_i32 s3, s1, 31
-; GCN-NEXT: s_add_i32 s0, s0, s2
-; GCN-NEXT: s_lshr_b32 s2, s3, 20
-; GCN-NEXT: s_add_i32 s1, s1, s2
-; GCN-NEXT: s_ashr_i32 s0, s0, 12
-; GCN-NEXT: s_ashr_i32 s1, s1, 12
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_v2i32_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s2, s0, 31
+; GFX6-NEXT: s_lshr_b32 s2, s2, 20
+; GFX6-NEXT: s_ashr_i32 s3, s1, 31
+; GFX6-NEXT: s_add_i32 s0, s0, s2
+; GFX6-NEXT: s_lshr_b32 s2, s3, 20
+; GFX6-NEXT: s_add_i32 s1, s1, s2
+; GFX6-NEXT: s_ashr_i32 s0, s0, 12
+; GFX6-NEXT: s_ashr_i32 s1, s1, 12
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_v2i32_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s0, s4, 31
+; GFX9-NEXT: s_ashr_i32 s1, s5, 31
+; GFX9-NEXT: s_lshr_b32 s0, s0, 20
+; GFX9-NEXT: s_lshr_b32 s1, s1, 20
+; GFX9-NEXT: s_add_i32 s0, s4, s0
+; GFX9-NEXT: s_add_i32 s1, s5, s1
+; GFX9-NEXT: s_ashr_i32 s0, s0, 12
+; GFX9-NEXT: s_ashr_i32 s1, s1, 12
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = sdiv <2 x i32> %x, <i32 4096, i32 4096>
store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void
@@ -4436,26 +6355,46 @@ define amdgpu_kernel void @ssdiv_v2i32_mixed_pow2k_denom(<2 x i32> addrspace(1)*
; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: ssdiv_v2i32_mixed_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GCN-NEXT: v_mov_b32_e32 v0, 0x80080081
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mul_hi_i32 v0, s1, v0
-; GCN-NEXT: s_ashr_i32 s2, s0, 31
-; GCN-NEXT: s_lshr_b32 s2, s2, 20
-; GCN-NEXT: s_add_i32 s0, s0, s2
-; GCN-NEXT: v_add_i32_e32 v0, vcc, s1, v0
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v0
-; GCN-NEXT: v_ashrrev_i32_e32 v0, 11, v0
-; GCN-NEXT: s_ashr_i32 s0, s0, 12
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v0
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: ssdiv_v2i32_mixed_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x80080081
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mul_hi_i32 v0, s1, v0
+; GFX6-NEXT: s_ashr_i32 s2, s0, 31
+; GFX6-NEXT: s_lshr_b32 s2, s2, 20
+; GFX6-NEXT: s_add_i32 s0, s0, s2
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s1, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 31, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v0, 11, v0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 12
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: ssdiv_v2i32_mixed_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s0, s4, 31
+; GFX9-NEXT: s_mul_hi_i32 s1, s5, 0x80080081
+; GFX9-NEXT: s_lshr_b32 s0, s0, 20
+; GFX9-NEXT: s_add_i32 s1, s1, s5
+; GFX9-NEXT: s_add_i32 s0, s4, s0
+; GFX9-NEXT: s_lshr_b32 s4, s1, 31
+; GFX9-NEXT: s_ashr_i32 s1, s1, 11
+; GFX9-NEXT: s_ashr_i32 s0, s0, 12
+; GFX9-NEXT: s_add_i32 s1, s1, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = sdiv <2 x i32> %x, <i32 4096, i32 4095>
store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void
@@ -4549,76 +6488,146 @@ define amdgpu_kernel void @sdiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %ou
; CHECK-NEXT: store <2 x i32> [[TMP82]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_v2i32_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
-; GCN-NEXT: s_movk_i32 s10, 0x1000
-; GCN-NEXT: s_mov_b32 s13, 0x4f7ffffe
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b32 s2, s10, s2
-; GCN-NEXT: s_ashr_i32 s11, s2, 31
-; GCN-NEXT: s_add_i32 s2, s2, s11
-; GCN-NEXT: s_xor_b32 s12, s2, s11
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12
-; GCN-NEXT: s_lshl_b32 s0, s10, s3
-; GCN-NEXT: s_sub_i32 s3, 0, s12
-; GCN-NEXT: s_ashr_i32 s2, s0, 31
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: s_add_i32 s0, s0, s2
-; GCN-NEXT: s_xor_b32 s10, s0, s2
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s10
-; GCN-NEXT: v_mul_f32_e32 v0, s13, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: s_ashr_i32 s1, s8, 31
-; GCN-NEXT: s_add_i32 s0, s8, s1
-; GCN-NEXT: s_xor_b32 s0, s0, s1
-; GCN-NEXT: v_mul_lo_u32 v1, s3, v0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GCN-NEXT: s_xor_b32 s3, s1, s11
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s0, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s13, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mul_lo_u32 v2, v0, s12
-; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v0
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s0, v2
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v2
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s12, v2
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GCN-NEXT: s_sub_i32 s0, 0, s10
-; GCN-NEXT: v_mul_lo_u32 v3, s0, v1
-; GCN-NEXT: s_ashr_i32 s0, s9, 31
-; GCN-NEXT: s_add_i32 s1, s9, s0
-; GCN-NEXT: s_xor_b32 s1, s1, s0
-; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
-; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v0
-; GCN-NEXT: s_xor_b32 s2, s0, s2
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1
-; GCN-NEXT: v_mul_hi_u32 v1, s1, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v2
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GCN-NEXT: v_xor_b32_e32 v0, s3, v0
-; GCN-NEXT: v_mul_lo_u32 v2, v1, s10
-; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v1
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v2
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s10, v2
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GCN-NEXT: v_xor_b32_e32 v1, s2, v1
-; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s2, v1
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
+; GFX6-NEXT: s_movk_i32 s10, 0x1000
+; GFX6-NEXT: s_mov_b32 s13, 0x4f7ffffe
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b32 s2, s10, s2
+; GFX6-NEXT: s_ashr_i32 s11, s2, 31
+; GFX6-NEXT: s_add_i32 s2, s2, s11
+; GFX6-NEXT: s_xor_b32 s12, s2, s11
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12
+; GFX6-NEXT: s_lshl_b32 s0, s10, s3
+; GFX6-NEXT: s_sub_i32 s3, 0, s12
+; GFX6-NEXT: s_ashr_i32 s2, s0, 31
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: s_add_i32 s0, s0, s2
+; GFX6-NEXT: s_xor_b32 s10, s0, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s10
+; GFX6-NEXT: v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: s_ashr_i32 s1, s8, 31
+; GFX6-NEXT: s_add_i32 s0, s8, s1
+; GFX6-NEXT: s_xor_b32 s0, s0, s1
+; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: s_xor_b32 s3, s1, s11
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, s13, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s12
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v2
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s12, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
+; GFX6-NEXT: s_sub_i32 s0, 0, s10
+; GFX6-NEXT: v_mul_lo_u32 v3, s0, v1
+; GFX6-NEXT: s_ashr_i32 s0, s9, 31
+; GFX6-NEXT: s_add_i32 s1, s9, s0
+; GFX6-NEXT: s_xor_b32 s1, s1, s0
+; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT: s_xor_b32 s2, s0, s2
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
+; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s3, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, s10
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v2
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s10, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s2, v1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_v2i32_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
+; GFX9-NEXT: s_movk_i32 s8, 0x1000
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x2c
+; GFX9-NEXT: s_mov_b32 s11, 0x4f7ffffe
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b32 s2, s8, s2
+; GFX9-NEXT: s_ashr_i32 s9, s2, 31
+; GFX9-NEXT: s_add_i32 s2, s2, s9
+; GFX9-NEXT: s_xor_b32 s10, s2, s9
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s10
+; GFX9-NEXT: s_lshl_b32 s0, s8, s3
+; GFX9-NEXT: s_ashr_i32 s1, s0, 31
+; GFX9-NEXT: s_add_i32 s0, s0, s1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: s_xor_b32 s8, s0, s1
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8
+; GFX9-NEXT: s_sub_i32 s0, 0, s10
+; GFX9-NEXT: v_mul_f32_e32 v0, s11, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: s_sub_i32 s3, 0, s8
+; GFX9-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, s11, v1
+; GFX9-NEXT: s_ashr_i32 s0, s6, 31
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
+; GFX9-NEXT: s_add_i32 s2, s6, s0
+; GFX9-NEXT: s_xor_b32 s2, s2, s0
+; GFX9-NEXT: s_xor_b32 s0, s0, s9
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
+; GFX9-NEXT: s_ashr_i32 s3, s7, 31
+; GFX9-NEXT: v_mul_lo_u32 v4, v0, s10
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
+; GFX9-NEXT: v_sub_u32_e32 v4, s2, v4
+; GFX9-NEXT: s_add_i32 s2, s7, s3
+; GFX9-NEXT: s_xor_b32 s2, s2, s3
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v4
+; GFX9-NEXT: v_mul_hi_u32 v1, s2, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s10, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v4
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, s8
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0
+; GFX9-NEXT: v_subrev_u32_e32 v0, s0, v0
+; GFX9-NEXT: v_sub_u32_e32 v3, s2, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v4, s8, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
+; GFX9-NEXT: s_xor_b32 s0, s3, s1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_xor_b32_e32 v1, s0, v1
+; GFX9-NEXT: v_subrev_u32_e32 v1, s0, v1
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = sdiv <2 x i32> %x, %shl.y
store <2 x i32> %r, <2 x i32> addrspace(1)* %out
@@ -4631,23 +6640,40 @@ define amdgpu_kernel void @srem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_i32_oddk_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: v_mov_b32_e32 v0, 0xd9528441
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mul_hi_i32 v0, s0, v0
-; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v0
-; GCN-NEXT: v_ashrrev_i32_e32 v0, 20, v0
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_mul_i32_i24_e32 v0, 0x12d8fb, v0
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_i32_oddk_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: v_mov_b32_e32 v0, 0xd9528441
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mul_hi_i32 v0, s0, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 31, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v0, 20, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: v_mul_i32_i24_e32 v0, 0x12d8fb, v0
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_i32_oddk_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x12d8fb
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_mul_hi_i32 s0, s4, 0xd9528441
+; GFX9-NEXT: s_add_i32 s0, s0, s4
+; GFX9-NEXT: s_lshr_b32 s1, s0, 31
+; GFX9-NEXT: s_ashr_i32 s0, s0, 20
+; GFX9-NEXT: s_add_i32 s0, s0, s1
+; GFX9-NEXT: v_mul_i32_i24_e32 v1, s0, v1
+; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1
+; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = srem i32 %x, 1235195
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -4659,21 +6685,36 @@ define amdgpu_kernel void @srem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x)
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_i32_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: s_lshr_b32 s1, s1, 20
-; GCN-NEXT: s_add_i32 s1, s0, s1
-; GCN-NEXT: s_and_b32 s1, s1, 0xfffff000
-; GCN-NEXT: s_sub_i32 s0, s0, s1
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_i32_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s1, s0, 31
+; GFX6-NEXT: s_lshr_b32 s1, s1, 20
+; GFX6-NEXT: s_add_i32 s1, s0, s1
+; GFX6-NEXT: s_and_b32 s1, s1, 0xfffff000
+; GFX6-NEXT: s_sub_i32 s0, s0, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_i32_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s0, s4, 31
+; GFX9-NEXT: s_lshr_b32 s0, s0, 20
+; GFX9-NEXT: s_add_i32 s0, s4, s0
+; GFX9-NEXT: s_and_b32 s0, s0, 0xfffff000
+; GFX9-NEXT: s_sub_i32 s0, s4, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX9-NEXT: s_endpgm
%r = srem i32 %x, 4096
store i32 %r, i32 addrspace(1)* %out
ret void
@@ -4686,41 +6727,77 @@ define amdgpu_kernel void @srem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %
; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_i32_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b32 s3, 0x1000, s3
-; GCN-NEXT: s_ashr_i32 s4, s3, 31
-; GCN-NEXT: s_add_i32 s3, s3, s4
-; GCN-NEXT: s_xor_b32 s6, s3, s4
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GCN-NEXT: s_sub_i32 s3, 0, s6
-; GCN-NEXT: s_ashr_i32 s4, s2, 31
-; GCN-NEXT: s_add_i32 s2, s2, s4
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: s_xor_b32 s5, s2, s4
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_lo_u32 v1, s3, v0
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s5, v0
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s6
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
-; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-NEXT: v_xor_b32_e32 v0, s4, v0
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
-; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_i32_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s3
+; GFX6-NEXT: s_ashr_i32 s4, s3, 31
+; GFX6-NEXT: s_add_i32 s3, s3, s4
+; GFX6-NEXT: s_xor_b32 s6, s3, s4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GFX6-NEXT: s_sub_i32 s3, 0, s6
+; GFX6-NEXT: s_ashr_i32 s4, s2, 31
+; GFX6-NEXT: s_add_i32 s2, s2, s4
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: s_xor_b32 s5, s2, s4
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_i32_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s3
+; GFX9-NEXT: s_ashr_i32 s4, s3, 31
+; GFX9-NEXT: s_add_i32 s3, s3, s4
+; GFX9-NEXT: s_xor_b32 s3, s3, s4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
+; GFX9-NEXT: s_sub_i32 s4, 0, s3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX9-NEXT: s_ashr_i32 s4, s2, 31
+; GFX9-NEXT: s_add_i32 s2, s2, s4
+; GFX9-NEXT: s_xor_b32 s2, s2, s4
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_subrev_u32_e32 v0, s4, v0
+; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9-NEXT: s_endpgm
%shl.y = shl i32 4096, %y
%r = srem i32 %x, %shl.y
store i32 %r, i32 addrspace(1)* %out
@@ -4738,28 +6815,50 @@ define amdgpu_kernel void @srem_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out,
; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_v2i32_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GCN-NEXT: s_movk_i32 s2, 0xf000
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s3, s0, 31
-; GCN-NEXT: s_lshr_b32 s3, s3, 20
-; GCN-NEXT: s_add_i32 s3, s0, s3
-; GCN-NEXT: s_and_b32 s3, s3, s2
-; GCN-NEXT: s_sub_i32 s0, s0, s3
-; GCN-NEXT: s_ashr_i32 s3, s1, 31
-; GCN-NEXT: s_lshr_b32 s3, s3, 20
-; GCN-NEXT: s_add_i32 s3, s1, s3
-; GCN-NEXT: s_and_b32 s2, s3, s2
-; GCN-NEXT: s_sub_i32 s1, s1, s2
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_v2i32_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT: s_movk_i32 s2, 0xf000
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s3, s0, 31
+; GFX6-NEXT: s_lshr_b32 s3, s3, 20
+; GFX6-NEXT: s_add_i32 s3, s0, s3
+; GFX6-NEXT: s_and_b32 s3, s3, s2
+; GFX6-NEXT: s_sub_i32 s0, s0, s3
+; GFX6-NEXT: s_ashr_i32 s3, s1, 31
+; GFX6-NEXT: s_lshr_b32 s3, s3, 20
+; GFX6-NEXT: s_add_i32 s3, s1, s3
+; GFX6-NEXT: s_and_b32 s2, s3, s2
+; GFX6-NEXT: s_sub_i32 s1, s1, s2
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_v2i32_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: s_movk_i32 s6, 0xf000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s0, s4, 31
+; GFX9-NEXT: s_ashr_i32 s1, s5, 31
+; GFX9-NEXT: s_lshr_b32 s0, s0, 20
+; GFX9-NEXT: s_lshr_b32 s1, s1, 20
+; GFX9-NEXT: s_add_i32 s0, s4, s0
+; GFX9-NEXT: s_add_i32 s1, s5, s1
+; GFX9-NEXT: s_and_b32 s0, s0, s6
+; GFX9-NEXT: s_and_b32 s1, s1, s6
+; GFX9-NEXT: s_sub_i32 s0, s4, s0
+; GFX9-NEXT: s_sub_i32 s1, s5, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = srem <2 x i32> %x, <i32 4096, i32 4096>
store <2 x i32> %r, <2 x i32> addrspace(1)* %out
ret void
@@ -4847,71 +6946,135 @@ define amdgpu_kernel void @srem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %ou
; CHECK-NEXT: store <2 x i32> [[TMP76]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_v2i32_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
-; GCN-NEXT: s_movk_i32 s6, 0x1000
-; GCN-NEXT: s_mov_b32 s10, 0x4f7ffffe
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b32 s2, s6, s2
-; GCN-NEXT: s_ashr_i32 s4, s2, 31
-; GCN-NEXT: s_add_i32 s2, s2, s4
-; GCN-NEXT: s_xor_b32 s9, s2, s4
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9
-; GCN-NEXT: s_lshl_b32 s2, s6, s3
-; GCN-NEXT: s_ashr_i32 s6, s2, 31
-; GCN-NEXT: s_add_i32 s2, s2, s6
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: s_sub_i32 s8, 0, s9
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GCN-NEXT: v_mul_f32_e32 v0, s10, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s3, s0, 31
-; GCN-NEXT: s_add_i32 s0, s0, s3
-; GCN-NEXT: v_mul_lo_u32 v1, s8, v0
-; GCN-NEXT: s_xor_b32 s8, s2, s6
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s8
-; GCN-NEXT: s_xor_b32 s0, s0, s3
-; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-NEXT: s_sub_i32 s2, 0, s8
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s0, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s10, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s9
-; GCN-NEXT: v_mul_lo_u32 v2, s2, v1
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: s_ashr_i32 s0, s1, 31
-; GCN-NEXT: v_mul_hi_u32 v2, v1, v2
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s9, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v0
-; GCN-NEXT: s_add_i32 s1, s1, s0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GCN-NEXT: s_xor_b32 s1, s1, s0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; GCN-NEXT: v_mul_hi_u32 v1, s1, v1
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s9, v0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s8
-; GCN-NEXT: v_xor_b32_e32 v0, s3, v0
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
-; GCN-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s8, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s8, v1
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GCN-NEXT: v_xor_b32_e32 v1, s0, v1
-; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s0, v1
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_v2i32_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
+; GFX6-NEXT: s_movk_i32 s6, 0x1000
+; GFX6-NEXT: s_mov_b32 s10, 0x4f7ffffe
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b32 s2, s6, s2
+; GFX6-NEXT: s_ashr_i32 s4, s2, 31
+; GFX6-NEXT: s_add_i32 s2, s2, s4
+; GFX6-NEXT: s_xor_b32 s9, s2, s4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s9
+; GFX6-NEXT: s_lshl_b32 s2, s6, s3
+; GFX6-NEXT: s_ashr_i32 s6, s2, 31
+; GFX6-NEXT: s_add_i32 s2, s2, s6
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: s_sub_i32 s8, 0, s9
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT: v_mul_f32_e32 v0, s10, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s3, s0, 31
+; GFX6-NEXT: s_add_i32 s0, s0, s3
+; GFX6-NEXT: v_mul_lo_u32 v1, s8, v0
+; GFX6-NEXT: s_xor_b32 s8, s2, s6
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s8
+; GFX6-NEXT: s_xor_b32 s0, s0, s3
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT: s_sub_i32 s2, 0, s8
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, s10, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s9
+; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: s_ashr_i32 s0, s1, 31
+; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v0
+; GFX6-NEXT: s_add_i32 s1, s1, s0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: s_xor_b32 s1, s1, s0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s8
+; GFX6-NEXT: v_xor_b32_e32 v0, s3, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_xor_b32_e32 v1, s0, v1
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s0, v1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_v2i32_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34
+; GFX9-NEXT: s_movk_i32 s8, 0x1000
+; GFX9-NEXT: s_mov_b32 s9, 0x4f7ffffe
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b32 s0, s8, s6
+; GFX9-NEXT: s_ashr_i32 s1, s0, 31
+; GFX9-NEXT: s_add_i32 s0, s0, s1
+; GFX9-NEXT: s_xor_b32 s0, s0, s1
+; GFX9-NEXT: s_lshl_b32 s1, s8, s7
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s0
+; GFX9-NEXT: s_ashr_i32 s6, s1, 31
+; GFX9-NEXT: s_add_i32 s1, s1, s6
+; GFX9-NEXT: s_xor_b32 s1, s1, s6
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: s_sub_i32 s7, 0, s0
+; GFX9-NEXT: s_ashr_i32 s6, s4, 31
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_f32_e32 v0, s9, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: s_add_i32 s4, s4, s6
+; GFX9-NEXT: v_mul_f32_e32 v1, s9, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_lo_u32 v2, s7, v0
+; GFX9-NEXT: s_sub_i32 s7, 0, s1
+; GFX9-NEXT: s_xor_b32 s4, s4, s6
+; GFX9-NEXT: v_mul_lo_u32 v3, s7, v1
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: s_ashr_i32 s7, s5, 31
+; GFX9-NEXT: s_add_i32 s5, s5, s7
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX9-NEXT: s_xor_b32 s5, s5, s7
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s1
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
+; GFX9-NEXT: v_subrev_u32_e32 v3, s0, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s0, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s0, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s1, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s1, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX9-NEXT: v_xor_b32_e32 v1, s7, v1
+; GFX9-NEXT: v_subrev_u32_e32 v0, s6, v0
+; GFX9-NEXT: v_subrev_u32_e32 v1, s7, v1
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y
%r = srem <2 x i32> %x, %shl.y
store <2 x i32> %r, <2 x i32> addrspace(1)* %out
@@ -4924,130 +7087,251 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_i64_oddk_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_mov_b32_e32 v0, 0x4f176a73
-; GCN-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GCN-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_movk_i32 s2, 0xfee0
-; GCN-NEXT: s_mov_b32 s3, 0x68958c89
-; GCN-NEXT: v_mov_b32_e32 v8, 0
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mov_b32_e32 v7, 0
-; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT: v_mul_lo_u32 v2, v0, s2
-; GCN-NEXT: v_mul_hi_u32 v3, v0, s3
-; GCN-NEXT: v_mul_lo_u32 v4, v1, s3
-; GCN-NEXT: s_mov_b32 s11, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s8, s4
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mul_lo_u32 v3, v0, s3
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v3
-; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: s_movk_i32 s4, 0x11e
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v3
-; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT: s_mov_b32 s10, -1
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v4, v0, s2
-; GCN-NEXT: v_mul_hi_u32 v5, v0, s3
-; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GCN-NEXT: v_mul_lo_u32 v6, v2, s3
-; GCN-NEXT: s_mov_b32 s2, 0x976a7377
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_mul_lo_u32 v5, v0, s3
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT: v_mul_lo_u32 v6, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v11, v2, v4
-; GCN-NEXT: s_movk_i32 s3, 0x11f
-; GCN-NEXT: s_mov_b32 s9, s5
-; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6
-; GCN-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
-; GCN-NEXT: v_mul_lo_u32 v10, v2, v5
-; GCN-NEXT: v_mul_hi_u32 v5, v2, v5
-; GCN-NEXT: v_mul_lo_u32 v2, v2, v4
-; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, s6, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s6, v0
-; GCN-NEXT: v_mul_hi_u32 v4, s6, v1
-; GCN-NEXT: v_mul_hi_u32 v5, s7, v1
-; GCN-NEXT: v_mul_lo_u32 v1, s7, v1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v4, s7, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s7, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v0, s3
-; GCN-NEXT: v_mul_hi_u32 v3, v0, s2
-; GCN-NEXT: v_mul_lo_u32 v4, v1, s2
-; GCN-NEXT: v_mov_b32_e32 v5, s3
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mul_lo_u32 v3, v0, s2
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT: v_sub_i32_e32 v4, vcc, s7, v2
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s6, v3
-; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3
-; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
-; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s4, v4
-; GCN-NEXT: s_mov_b32 s2, 0x976a7376
-; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s2, v5
-; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4
-; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
-; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
-; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
-; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
-; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v6, s7
-; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2
-; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s2, v3
-; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2
-; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_i64_oddk_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f176a73
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; GFX6-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: s_movk_i32 s2, 0xfee0
+; GFX6-NEXT: s_mov_b32 s3, 0x68958c89
+; GFX6-NEXT: v_mov_b32_e32 v8, 0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mov_b32_e32 v7, 0
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3
+; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3
+; GFX6-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s4
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v6, v0, v3
+; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT: s_movk_i32 s4, 0x11e
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
+; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT: s_mov_b32 s10, -1
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2
+; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3
+; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
+; GFX6-NEXT: v_mul_lo_u32 v6, v2, s3
+; GFX6-NEXT: s_mov_b32 s2, 0x976a7377
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, s3
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GFX6-NEXT: v_mul_lo_u32 v6, v0, v4
+; GFX6-NEXT: v_mul_hi_u32 v10, v0, v4
+; GFX6-NEXT: v_mul_hi_u32 v9, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v11, v2, v4
+; GFX6-NEXT: s_movk_i32 s3, 0x11f
+; GFX6-NEXT: s_mov_b32 s9, s5
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
+; GFX6-NEXT: v_mul_lo_u32 v10, v2, v5
+; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v10
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
+; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1
+; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s3
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, s2
+; GFX6-NEXT: v_mul_lo_u32 v4, v1, s2
+; GFX6-NEXT: v_mov_b32_e32 v5, s3
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, s2
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s7, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s6, v3
+; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
+; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3
+; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
+; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s4, v4
+; GFX6-NEXT: s_mov_b32 s2, 0x976a7376
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s2, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
+; GFX6-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
+; GFX6-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
+; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
+; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v6, s7
+; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s2, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_i64_oddk_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f176a73
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_movk_i32 s4, 0xfee0
+; GFX9-NEXT: s_mov_b32 s5, 0x68958c89
+; GFX9-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_movk_i32 s8, 0x11f
+; GFX9-NEXT: s_mov_b32 s9, 0x976a7376
+; GFX9-NEXT: v_mul_lo_u32 v2, v0, s4
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, s5
+; GFX9-NEXT: v_mul_lo_u32 v4, v0, s5
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, s5
+; GFX9-NEXT: v_mul_lo_u32 v8, v2, s5
+; GFX9-NEXT: v_mul_lo_u32 v9, v0, s5
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX9-NEXT: v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v8
+; GFX9-NEXT: v_mul_lo_u32 v7, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v9
+; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v10, vcc
+; GFX9-NEXT: v_mul_lo_u32 v10, v2, v9
+; GFX9-NEXT: v_mul_hi_u32 v9, v2, v9
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v8, v9, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v7, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX9-NEXT: s_mov_b32 s2, 0x976a7377
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v0, s8
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, s2
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, s2
+; GFX9-NEXT: v_mov_b32_e32 v5, s8
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, s2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_sub_u32_e32 v4, s7, v2
+; GFX9-NEXT: v_sub_co_u32_e64 v3, s[0:1], s6, v3
+; GFX9-NEXT: v_subb_co_u32_e64 v4, vcc, v4, v5, s[0:1]
+; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s2, v3
+; GFX9-NEXT: v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
+; GFX9-NEXT: s_movk_i32 s6, 0x11e
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s9, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s8, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, 2, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v7, s7
+; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v7, v2, s[0:1]
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s9, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s8, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v5, s[2:3]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[4:5]
+; GFX9-NEXT: s_endpgm
%r = udiv i64 %x, 1235195949943
store i64 %r, i64 addrspace(1)* %out
ret void
@@ -5059,19 +7343,30 @@ define amdgpu_kernel void @udiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x)
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_i64_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, s0
-; GCN-NEXT: s_mov_b32 s5, s1
-; GCN-NEXT: s_lshr_b64 s[0:1], s[2:3], 12
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_i64_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_lshr_b64 s[0:1], s[2:3], 12
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_i64_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 12
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9-NEXT: s_endpgm
%r = udiv i64 %x, 4096
store i64 %r, i64 addrspace(1)* %out
ret void
@@ -5084,21 +7379,34 @@ define amdgpu_kernel void @udiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_i64_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s8, s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s0, s4
-; GCN-NEXT: s_add_i32 s8, s8, 12
-; GCN-NEXT: s_mov_b32 s1, s5
-; GCN-NEXT: s_lshr_b64 s[4:5], s[6:7], s8
-; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_i64_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s8, s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_add_i32 s8, s8, 12
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_lshr_b64 s[4:5], s[6:7], s8
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_i64_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s2, s[0:1], 0x34
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_add_i32 s2, s2, 12
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX9-NEXT: s_endpgm
%shl.y = shl i64 4096, %y
%r = udiv i64 %x, %shl.y
store i64 %r, i64 addrspace(1)* %out
@@ -5116,21 +7424,36 @@ define amdgpu_kernel void @udiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_v2i64_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 12
-; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], 12
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: v_mov_b32_e32 v2, s2
-; GCN-NEXT: v_mov_b32_e32 v3, s3
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_v2i64_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], 12
+; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], 12
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_v2i64_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 12
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[6:7], 12
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = udiv <2 x i64> %x, <i64 4096, i64 4096>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void
@@ -5147,117 +7470,228 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)*
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_v2i64_mixed_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
-; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_movk_i32 s6, 0xf001
-; GCN-NEXT: v_mov_b32_e32 v7, 0
-; GCN-NEXT: v_mov_b32_e32 v2, 0
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-NEXT: s_movk_i32 s0, 0xfff
-; GCN-NEXT: v_mul_hi_u32 v3, v0, s6
-; GCN-NEXT: v_mul_lo_u32 v5, v1, s6
-; GCN-NEXT: v_mul_lo_u32 v4, v0, s6
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, v0, v3
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v4
-; GCN-NEXT: v_mul_lo_u32 v5, v0, v3
-; GCN-NEXT: v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT: v_mul_hi_u32 v9, v1, v3
-; GCN-NEXT: v_mul_lo_u32 v3, v1, v3
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc
-; GCN-NEXT: v_mul_lo_u32 v8, v1, v4
-; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v2, vcc
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v3
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GCN-NEXT: v_mul_hi_u32 v5, v0, s6
-; GCN-NEXT: v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
-; GCN-NEXT: v_mul_lo_u32 v6, v3, s6
-; GCN-NEXT: v_mul_lo_u32 v8, v0, s6
-; GCN-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; GCN-NEXT: v_mul_lo_u32 v6, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v9, v0, v8
-; GCN-NEXT: v_mul_hi_u32 v10, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v11, v3, v5
-; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6
-; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc
-; GCN-NEXT: v_mul_lo_u32 v10, v3, v8
-; GCN-NEXT: v_mul_hi_u32 v8, v3, v8
-; GCN-NEXT: v_mul_lo_u32 v3, v3, v5
-; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10
-; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v8, vcc
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v11, v2, vcc
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4
-; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mul_lo_u32 v3, s10, v1
-; GCN-NEXT: v_mul_hi_u32 v4, s10, v0
-; GCN-NEXT: v_mul_hi_u32 v5, s10, v1
-; GCN-NEXT: v_mul_hi_u32 v6, s11, v1
-; GCN-NEXT: v_mul_lo_u32 v1, s11, v1
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GCN-NEXT: v_mul_lo_u32 v5, s11, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
-; GCN-NEXT: s_lshr_b64 s[2:3], s[8:9], 12
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v2, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v2, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v1, s0
-; GCN-NEXT: v_mul_hi_u32 v3, v0, s0
-; GCN-NEXT: v_mul_lo_u32 v4, v0, s0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mov_b32_e32 v3, s11
-; GCN-NEXT: v_sub_i32_e32 v4, vcc, s10, v4
-; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s0, v4
-; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
-; GCN-NEXT: s_movk_i32 s0, 0xffe
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3
-; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0
-; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
-; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0
-; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4
-; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: v_mov_b32_e32 v1, s3
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: s_movk_i32 s6, 0xf001
+; GFX6-NEXT: v_mov_b32_e32 v7, 0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT: s_movk_i32 s0, 0xfff
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, s6
+; GFX6-NEXT: v_mul_lo_u32 v5, v1, s6
+; GFX6-NEXT: v_mul_lo_u32 v4, v0, s6
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, v0, v3
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v3
+; GFX6-NEXT: v_mul_hi_u32 v8, v0, v3
+; GFX6-NEXT: v_mul_hi_u32 v9, v1, v3
+; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc
+; GFX6-NEXT: v_mul_lo_u32 v8, v1, v4
+; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v2, vcc
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT: v_add_i32_e64 v0, s[2:3], v0, v3
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
+; GFX6-NEXT: v_mul_hi_u32 v5, v0, s6
+; GFX6-NEXT: v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
+; GFX6-NEXT: v_mul_lo_u32 v6, v3, s6
+; GFX6-NEXT: v_mul_lo_u32 v8, v0, s6
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
+; GFX6-NEXT: v_mul_lo_u32 v6, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v9, v0, v8
+; GFX6-NEXT: v_mul_hi_u32 v10, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v11, v3, v5
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc
+; GFX6-NEXT: v_mul_lo_u32 v10, v3, v8
+; GFX6-NEXT: v_mul_hi_u32 v8, v3, v8
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, v5
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v10
+; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v9, v8, vcc
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v11, v2, vcc
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
+; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mul_lo_u32 v3, s10, v1
+; GFX6-NEXT: v_mul_hi_u32 v4, s10, v0
+; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1
+; GFX6-NEXT: v_mul_hi_u32 v6, s11, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0
+; GFX6-NEXT: s_lshr_b64 s[2:3], s[8:9], 12
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v6, v2, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v7, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, s0
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, s0
+; GFX6-NEXT: v_mul_lo_u32 v4, v0, s0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, s11
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s10, v4
+; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s0, v4
+; GFX6-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
+; GFX6-NEXT: s_movk_i32 s0, 0xffe
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 2, v0
+; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, 1, v0
+; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_mov_b32_e32 v1, s3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_movk_i32 s4, 0xf001
+; GFX9-NEXT: v_mov_b32_e32 v7, 0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_movk_i32 s8, 0xfff
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, s4
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, s4
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, s4
+; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_mul_hi_u32 v6, v0, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v8, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX9-NEXT: v_mul_hi_u32 v4, v0, s4
+; GFX9-NEXT: v_mul_lo_u32 v6, v2, s4
+; GFX9-NEXT: v_mul_lo_u32 v8, v0, s4
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT: v_sub_u32_e32 v4, v4, v0
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v6
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v9, v0, v8
+; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v9, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v7, v10, vcc
+; GFX9-NEXT: v_mul_lo_u32 v10, v2, v8
+; GFX9-NEXT: v_mul_hi_u32 v8, v2, v8
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], 12
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8
+; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s6, v4
+; GFX9-NEXT: s_movk_i32 s6, 0xffe
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
+; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s8, v4
+; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 2, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1]
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v8, v6, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: global_store_dwordx4 v5, v[0:3], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = udiv <2 x i64> %x, <i64 4096, i64 4095>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void
@@ -5277,24 +7711,42 @@ define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: udiv_v2i64_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_add_i32 s0, s0, 12
-; GCN-NEXT: s_add_i32 s2, s2, 12
-; GCN-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
-; GCN-NEXT: s_lshr_b64 s[2:3], s[10:11], s2
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: v_mov_b32_e32 v2, s2
-; GCN-NEXT: v_mov_b32_e32 v3, s3
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: udiv_v2i64_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_add_i32 s0, s0, 12
+; GFX6-NEXT: s_add_i32 s2, s2, 12
+; GFX6-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
+; GFX6-NEXT: s_lshr_b64 s[2:3], s[10:11], s2
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: udiv_v2i64_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x44
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_add_i32 s0, s8, 12
+; GFX9-NEXT: s_add_i32 s8, s10, 12
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], s0
+; GFX9-NEXT: s_lshr_b64 s[4:5], s[6:7], s8
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = udiv <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out
@@ -5307,129 +7759,249 @@ define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_i64_oddk_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_mov_b32_e32 v0, 0x4f1761f8
-; GCN-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GCN-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_movk_i32 s2, 0xfee0
-; GCN-NEXT: s_mov_b32 s3, 0x689e0837
-; GCN-NEXT: v_mov_b32_e32 v8, 0
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mov_b32_e32 v7, 0
-; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT: v_mul_lo_u32 v2, v0, s2
-; GCN-NEXT: v_mul_hi_u32 v3, v0, s3
-; GCN-NEXT: v_mul_lo_u32 v4, v1, s3
-; GCN-NEXT: s_movk_i32 s12, 0x11f
-; GCN-NEXT: s_mov_b32 s13, 0x9761f7c9
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mul_lo_u32 v3, v0, s3
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v3
-; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s9, s5
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v3
-; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT: s_movk_i32 s5, 0x11e
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v4, v0, s2
-; GCN-NEXT: v_mul_hi_u32 v5, v0, s3
-; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GCN-NEXT: v_mul_lo_u32 v6, v2, s3
-; GCN-NEXT: s_mov_b32 s8, s4
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_mul_lo_u32 v5, v0, s3
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT: v_mul_lo_u32 v6, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v11, v2, v4
-; GCN-NEXT: s_mov_b32 s4, 0x9761f7c8
-; GCN-NEXT: s_mov_b32 s11, 0xf000
-; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6
-; GCN-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
-; GCN-NEXT: v_mul_lo_u32 v10, v2, v5
-; GCN-NEXT: v_mul_hi_u32 v5, v2, v5
-; GCN-NEXT: v_mul_lo_u32 v2, v2, v4
-; GCN-NEXT: s_mov_b32 s10, -1
-; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, s6, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s6, v0
-; GCN-NEXT: v_mul_hi_u32 v4, s6, v1
-; GCN-NEXT: v_mul_hi_u32 v5, s7, v1
-; GCN-NEXT: v_mul_lo_u32 v1, s7, v1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v4, s7, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s7, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v0, s12
-; GCN-NEXT: v_mul_hi_u32 v3, v0, s13
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s13
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s13
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s7, v1
-; GCN-NEXT: v_mov_b32_e32 v3, s12
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
-; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
-; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s13, v0
-; GCN-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
-; GCN-NEXT: v_cmp_lt_u32_e64 s[2:3], s5, v5
-; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3]
-; GCN-NEXT: v_cmp_lt_u32_e64 s[2:3], s4, v4
-; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s13, v4
-; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s12, v5
-; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3]
-; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
-; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v5, s7
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s5, v1
-; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
-; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s12, v1
-; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_i64_oddk_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f1761f8
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; GFX6-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: s_movk_i32 s2, 0xfee0
+; GFX6-NEXT: s_mov_b32 s3, 0x689e0837
+; GFX6-NEXT: v_mov_b32_e32 v8, 0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mov_b32_e32 v7, 0
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3
+; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3
+; GFX6-NEXT: s_movk_i32 s12, 0x11f
+; GFX6-NEXT: s_mov_b32 s13, 0x9761f7c9
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v6, v0, v3
+; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s9, s5
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
+; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT: s_movk_i32 s5, 0x11e
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2
+; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3
+; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
+; GFX6-NEXT: v_mul_lo_u32 v6, v2, s3
+; GFX6-NEXT: s_mov_b32 s8, s4
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, s3
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GFX6-NEXT: v_mul_lo_u32 v6, v0, v4
+; GFX6-NEXT: v_mul_hi_u32 v10, v0, v4
+; GFX6-NEXT: v_mul_hi_u32 v9, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v11, v2, v4
+; GFX6-NEXT: s_mov_b32 s4, 0x9761f7c8
+; GFX6-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
+; GFX6-NEXT: v_mul_lo_u32 v10, v2, v5
+; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX6-NEXT: s_mov_b32 s10, -1
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v10
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
+; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1
+; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s12
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, s13
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s13
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s13
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s7, v1
+; GFX6-NEXT: v_mov_b32_e32 v3, s12
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
+; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
+; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s13, v0
+; GFX6-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
+; GFX6-NEXT: v_cmp_lt_u32_e64 s[2:3], s5, v5
+; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3]
+; GFX6-NEXT: v_cmp_lt_u32_e64 s[2:3], s4, v4
+; GFX6-NEXT: v_subrev_i32_e64 v3, s[0:1], s13, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s12, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3]
+; GFX6-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v5, s7
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s5, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s12, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_i64_oddk_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f1761f8
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_movk_i32 s4, 0xfee0
+; GFX9-NEXT: s_mov_b32 s5, 0x689e0837
+; GFX9-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_movk_i32 s8, 0x11f
+; GFX9-NEXT: s_mov_b32 s9, 0x9761f7c9
+; GFX9-NEXT: v_mul_lo_u32 v2, v0, s4
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, s5
+; GFX9-NEXT: v_mul_lo_u32 v4, v0, s5
+; GFX9-NEXT: s_mov_b32 s10, 0x9761f7c8
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, s5
+; GFX9-NEXT: v_mul_lo_u32 v8, v2, s5
+; GFX9-NEXT: v_mul_lo_u32 v9, v0, s5
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX9-NEXT: v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v8
+; GFX9-NEXT: v_mul_lo_u32 v7, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v9
+; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v10, vcc
+; GFX9-NEXT: v_mul_lo_u32 v10, v2, v9
+; GFX9-NEXT: v_mul_hi_u32 v9, v2, v9
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v8, v9, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v7, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v0, s8
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, s9
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s9
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s9
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT: v_sub_co_u32_e64 v0, s[0:1], s6, v0
+; GFX9-NEXT: v_sub_u32_e32 v2, s7, v1
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v2, v3, s[0:1]
+; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[2:3], s9, v0
+; GFX9-NEXT: v_subbrev_co_u32_e64 v5, vcc, 0, v2, s[2:3]
+; GFX9-NEXT: s_movk_i32 s6, 0x11e
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s10, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s8, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v2, v3, s[2:3]
+; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s9, v4
+; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v5, s7
+; GFX9-NEXT: v_subb_co_u32_e64 v1, vcc, v5, v1, s[0:1]
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s10, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s8, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[2:3]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[4:5]
+; GFX9-NEXT: s_endpgm
%r = urem i64 %x, 1235195393993
store i64 %r, i64 addrspace(1)* %out
ret void
@@ -5441,19 +8013,29 @@ define amdgpu_kernel void @urem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x)
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_i64_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s0, s4
-; GCN-NEXT: s_and_b32 s4, s6, 0xfff
-; GCN-NEXT: s_mov_b32 s1, s5
-; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_i64_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_and_b32 s4, s6, 0xfff
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_i64_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s2, s2, 0xfff
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX9-NEXT: s_endpgm
%r = urem i64 %x, 4096
store i64 %r, i64 addrspace(1)* %out
ret void
@@ -5466,25 +8048,42 @@ define amdgpu_kernel void @urem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_i64_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT: s_load_dword s8, s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s0, s4
-; GCN-NEXT: s_mov_b32 s1, s5
-; GCN-NEXT: s_mov_b32 s5, 0
-; GCN-NEXT: s_movk_i32 s4, 0x1000
-; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], s8
-; GCN-NEXT: s_add_u32 s4, s4, -1
-; GCN-NEXT: s_addc_u32 s5, s5, -1
-; GCN-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
-; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_i64_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s8, s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_mov_b32 s5, 0
+; GFX6-NEXT: s_movk_i32 s4, 0x1000
+; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], s8
+; GFX6-NEXT: s_add_u32 s4, s4, -1
+; GFX6-NEXT: s_addc_u32 s5, s5, -1
+; GFX6-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_i64_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX9-NEXT: s_load_dword s2, s[0:1], 0x34
+; GFX9-NEXT: s_mov_b32 s1, 0
+; GFX9-NEXT: s_movk_i32 s0, 0x1000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
+; GFX9-NEXT: s_add_u32 s0, s0, -1
+; GFX9-NEXT: s_addc_u32 s1, s1, -1
+; GFX9-NEXT: s_and_b64 s[0:1], s[6:7], s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX9-NEXT: s_endpgm
%shl.y = shl i64 4096, %y
%r = urem i64 %x, %shl.y
store i64 %r, i64 addrspace(1)* %out
@@ -5502,22 +8101,37 @@ define amdgpu_kernel void @urem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_v2i64_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
-; GCN-NEXT: s_movk_i32 s8, 0xfff
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_and_b32 s0, s0, s8
-; GCN-NEXT: s_and_b32 s1, s2, s8
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v2, s1
-; GCN-NEXT: v_mov_b32_e32 v3, v1
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_v2i64_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX6-NEXT: s_movk_i32 s8, 0xfff
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s0, s0, s8
+; GFX6-NEXT: s_and_b32 s1, s2, s8
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_v2i64_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT: s_movk_i32 s0, 0xfff
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mov_b32_e32 v3, v1
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s1, s4, s0
+; GFX9-NEXT: s_and_b32 s0, s6, s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
+; GFX9-NEXT: global_store_dwordx4 v1, v[0:3], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = urem <2 x i64> %x, <i64 4096, i64 4096>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void
@@ -5537,30 +8151,54 @@ define amdgpu_kernel void @urem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: urem_v2i64_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11
-; GCN-NEXT: s_mov_b32 s13, 0
-; GCN-NEXT: s_movk_i32 s12, 0x1000
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b64 s[2:3], s[12:13], s2
-; GCN-NEXT: s_lshl_b64 s[0:1], s[12:13], s0
-; GCN-NEXT: s_add_u32 s0, s0, -1
-; GCN-NEXT: s_addc_u32 s1, s1, -1
-; GCN-NEXT: s_and_b64 s[0:1], s[8:9], s[0:1]
-; GCN-NEXT: s_add_u32 s2, s2, -1
-; GCN-NEXT: s_addc_u32 s3, s3, -1
-; GCN-NEXT: s_and_b64 s[2:3], s[10:11], s[2:3]
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: v_mov_b32_e32 v2, s2
-; GCN-NEXT: v_mov_b32_e32 v3, s3
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: urem_v2i64_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11
+; GFX6-NEXT: s_mov_b32 s13, 0
+; GFX6-NEXT: s_movk_i32 s12, 0x1000
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b64 s[2:3], s[12:13], s2
+; GFX6-NEXT: s_lshl_b64 s[0:1], s[12:13], s0
+; GFX6-NEXT: s_add_u32 s0, s0, -1
+; GFX6-NEXT: s_addc_u32 s1, s1, -1
+; GFX6-NEXT: s_and_b64 s[0:1], s[8:9], s[0:1]
+; GFX6-NEXT: s_add_u32 s2, s2, -1
+; GFX6-NEXT: s_addc_u32 s3, s3, -1
+; GFX6-NEXT: s_and_b64 s[2:3], s[10:11], s[2:3]
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: urem_v2i64_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x44
+; GFX9-NEXT: s_mov_b32 s1, 0
+; GFX9-NEXT: s_movk_i32 s0, 0x1000
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], s10
+; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s8
+; GFX9-NEXT: s_add_u32 s0, s0, -1
+; GFX9-NEXT: s_addc_u32 s1, s1, -1
+; GFX9-NEXT: s_and_b64 s[0:1], s[4:5], s[0:1]
+; GFX9-NEXT: s_add_u32 s4, s10, -1
+; GFX9-NEXT: s_addc_u32 s5, s11, -1
+; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = urem <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out
@@ -5573,125 +8211,241 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_i64_oddk_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
-; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_mov_b32 s2, 0xffed2705
-; GCN-NEXT: v_mov_b32_e32 v8, 0
-; GCN-NEXT: v_mov_b32_e32 v7, 0
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
-; GCN-NEXT: v_mul_lo_u32 v2, v1, s2
-; GCN-NEXT: v_mul_lo_u32 v4, v0, s2
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, s8
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
-; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v3, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
-; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
-; GCN-NEXT: s_mov_b32 s5, s9
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GCN-NEXT: v_mul_lo_u32 v4, v2, s2
-; GCN-NEXT: v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_mul_lo_u32 v5, v0, s2
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
-; GCN-NEXT: v_mul_lo_u32 v10, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v12, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v11, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v9, v2, v5
-; GCN-NEXT: v_mul_lo_u32 v5, v2, v5
-; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
-; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT: v_addc_u32_e32 v11, vcc, v8, v12, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v2, v4
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v10, v5
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v11, v9, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: s_ashr_i32 s2, s11, 31
-; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GCN-NEXT: s_add_u32 s0, s10, s2
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: s_mov_b32 s3, s2
-; GCN-NEXT: s_addc_u32 s1, s11, s2
-; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, s0, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s0, v0
-; GCN-NEXT: v_mul_hi_u32 v4, s0, v1
-; GCN-NEXT: v_mul_hi_u32 v5, s1, v1
-; GCN-NEXT: v_mul_lo_u32 v1, s1, v1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v4, s1, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
-; GCN-NEXT: s_mov_b32 s3, 0x12d8fb
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v1, s3
-; GCN-NEXT: v_mul_hi_u32 v3, s3, v0
-; GCN-NEXT: v_mul_lo_u32 v4, v0, s3
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_sub_i32_e32 v4, vcc, s0, v4
-; GCN-NEXT: v_mov_b32_e32 v3, s1
-; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s3, v4
-; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
-; GCN-NEXT: s_mov_b32 s0, 0x12d8fa
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3
-; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0
-; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
-; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0
-; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4
-; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
-; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GCN-NEXT: v_xor_b32_e32 v0, s2, v0
-; GCN-NEXT: v_xor_b32_e32 v1, s2, v1
-; GCN-NEXT: v_mov_b32_e32 v2, s2
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_i64_oddk_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s2, 0xffed2705
+; GFX6-NEXT: v_mov_b32_e32 v8, 0
+; GFX6-NEXT: v_mov_b32_e32 v7, 0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, s2
+; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, s8
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
+; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
+; GFX6-NEXT: s_mov_b32 s5, s9
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
+; GFX6-NEXT: v_mul_lo_u32 v4, v2, s2
+; GFX6-NEXT: v_mul_hi_u32 v5, s2, v0
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, s2
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
+; GFX6-NEXT: v_mul_lo_u32 v10, v0, v4
+; GFX6-NEXT: v_mul_hi_u32 v12, v0, v4
+; GFX6-NEXT: v_mul_hi_u32 v11, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v9, v2, v5
+; GFX6-NEXT: v_mul_lo_u32 v5, v2, v5
+; GFX6-NEXT: v_mul_hi_u32 v6, v2, v4
+; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_addc_u32_e32 v11, vcc, v8, v12, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v10, v5
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v11, v9, vcc
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: s_ashr_i32 s2, s11, 31
+; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
+; GFX6-NEXT: s_add_u32 s0, s10, s2
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: s_mov_b32 s3, s2
+; GFX6-NEXT: s_addc_u32 s1, s11, s2
+; GFX6-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX6-NEXT: v_mul_hi_u32 v4, s0, v1
+; GFX6-NEXT: v_mul_hi_u32 v5, s1, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT: s_mov_b32 s3, 0x12d8fb
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, s3
+; GFX6-NEXT: v_mul_hi_u32 v3, s3, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, v0, s3
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s0, v4
+; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v4
+; GFX6-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
+; GFX6-NEXT: s_mov_b32 s0, 0x12d8fa
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 2, v0
+; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, 1, v0
+; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
+; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_i64_oddk_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s8, 0xffed2705
+; GFX9-NEXT: v_mov_b32_e32 v7, 0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8
+; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX9-NEXT: v_mul_lo_u32 v4, v2, s8
+; GFX9-NEXT: v_mul_hi_u32 v6, s8, v0
+; GFX9-NEXT: v_mul_lo_u32 v8, v0, s8
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v4, v6, v4
+; GFX9-NEXT: v_sub_u32_e32 v4, v4, v0
+; GFX9-NEXT: v_mul_lo_u32 v10, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v11, v0, v8
+; GFX9-NEXT: v_mul_hi_u32 v12, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v9, v2, v8
+; GFX9-NEXT: v_mul_lo_u32 v8, v2, v8
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_mul_hi_u32 v6, v2, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v7, v12, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s2, s7, 31
+; GFX9-NEXT: s_add_u32 s0, s6, s2
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: s_mov_b32 s3, s2
+; GFX9-NEXT: s_addc_u32 s1, s7, s2
+; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v6, s1, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s1, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s1, v0
+; GFX9-NEXT: s_mov_b32 s3, 0x12d8fb
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, v0, s3
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, s3
+; GFX9-NEXT: v_mul_hi_u32 v3, s3, v0
+; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s0, v4
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
+; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s3, v4
+; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
+; GFX9-NEXT: s_mov_b32 s3, 0x12d8fa
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 2, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v6, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s2, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
+; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5]
+; GFX9-NEXT: s_endpgm
%r = sdiv i64 %x, 1235195
store i64 %r, i64 addrspace(1)* %out
ret void
@@ -5703,23 +8457,38 @@ define amdgpu_kernel void @sdiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x)
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_i64_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, s0
-; GCN-NEXT: s_ashr_i32 s0, s3, 31
-; GCN-NEXT: s_lshr_b32 s0, s0, 20
-; GCN-NEXT: s_add_u32 s0, s2, s0
-; GCN-NEXT: s_mov_b32 s5, s1
-; GCN-NEXT: s_addc_u32 s1, s3, 0
-; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_i64_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_ashr_i32 s0, s3, 31
+; GFX6-NEXT: s_lshr_b32 s0, s0, 20
+; GFX6-NEXT: s_add_u32 s0, s2, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_addc_u32 s1, s3, 0
+; GFX6-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_i64_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s4, s3, 31
+; GFX9-NEXT: s_lshr_b32 s4, s4, 20
+; GFX9-NEXT: s_add_u32 s2, s2, s4
+; GFX9-NEXT: s_addc_u32 s3, s3, 0
+; GFX9-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9-NEXT: s_endpgm
%r = sdiv i64 %x, 4096
store i64 %r, i64 addrspace(1)* %out
ret void
@@ -5732,146 +8501,284 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_i64_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dword s4, s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s3, 0
-; GCN-NEXT: s_movk_i32 s2, 0x1000
-; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GCN-NEXT: s_ashr_i32 s12, s3, 31
-; GCN-NEXT: s_add_u32 s2, s2, s12
-; GCN-NEXT: s_mov_b32 s13, s12
-; GCN-NEXT: s_addc_u32 s3, s3, s12
-; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13]
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3
-; GCN-NEXT: s_sub_u32 s4, 0, s2
-; GCN-NEXT: s_subb_u32 s5, 0, s3
-; GCN-NEXT: s_ashr_i32 s14, s11, 31
-; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_mov_b32 s15, s14
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s4, v0
-; GCN-NEXT: v_mul_lo_u32 v2, s4, v1
-; GCN-NEXT: v_mul_lo_u32 v5, s5, v0
-; GCN-NEXT: v_mul_lo_u32 v4, s4, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; GCN-NEXT: v_mul_hi_u32 v3, v0, v4
-; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
-; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GCN-NEXT: v_mov_b32_e32 v4, 0
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mov_b32_e32 v6, 0
-; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
-; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GCN-NEXT: v_mul_lo_u32 v5, s4, v2
-; GCN-NEXT: v_mul_hi_u32 v7, s4, v0
-; GCN-NEXT: v_mul_lo_u32 v8, s5, v0
-; GCN-NEXT: s_mov_b32 s5, s9
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
-; GCN-NEXT: v_mul_lo_u32 v7, s4, v0
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT: v_mul_lo_u32 v10, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v12, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT: v_mul_hi_u32 v9, v2, v7
-; GCN-NEXT: v_mul_lo_u32 v7, v2, v7
-; GCN-NEXT: v_mul_hi_u32 v8, v2, v5
-; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v2, v5
-; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
-; GCN-NEXT: s_add_u32 s0, s10, s14
-; GCN-NEXT: s_addc_u32 s1, s11, s14
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, s10, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s10, v0
-; GCN-NEXT: v_mul_hi_u32 v5, s10, v1
-; GCN-NEXT: v_mul_hi_u32 v7, s11, v1
-; GCN-NEXT: v_mul_lo_u32 v1, s11, v1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT: v_mul_lo_u32 v5, s11, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
-; GCN-NEXT: s_mov_b32 s4, s8
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, s2, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
-; GCN-NEXT: v_mul_lo_u32 v4, s3, v0
-; GCN-NEXT: v_mov_b32_e32 v5, s3
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mul_lo_u32 v3, s2, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v2
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s10, v3
-; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3
-; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4
-; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5
-; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4
-; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
-; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
-; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
-; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
-; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v6, s11
-; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
-; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
-; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2
-; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: s_xor_b64 s[0:1], s[14:15], s[12:13]
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
-; GCN-NEXT: v_xor_b32_e32 v1, s1, v1
-; GCN-NEXT: v_mov_b32_e32 v2, s1
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_i64_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dword s4, s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s3, 0
+; GFX6-NEXT: s_movk_i32 s2, 0x1000
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
+; GFX6-NEXT: s_ashr_i32 s12, s3, 31
+; GFX6-NEXT: s_add_u32 s2, s2, s12
+; GFX6-NEXT: s_mov_b32 s13, s12
+; GFX6-NEXT: s_addc_u32 s3, s3, s12
+; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13]
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3
+; GFX6-NEXT: s_sub_u32 s4, 0, s2
+; GFX6-NEXT: s_subb_u32 s5, 0, s3
+; GFX6-NEXT: s_ashr_i32 s14, s11, 31
+; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s15, s14
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s4, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1
+; GFX6-NEXT: v_mul_lo_u32 v5, s5, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s4, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
+; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mov_b32_e32 v6, 0
+; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
+; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
+; GFX6-NEXT: v_mul_lo_u32 v5, s4, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, s4, v0
+; GFX6-NEXT: v_mul_lo_u32 v8, s5, v0
+; GFX6-NEXT: s_mov_b32 s5, s9
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GFX6-NEXT: v_mul_lo_u32 v7, s4, v0
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5
+; GFX6-NEXT: v_mul_lo_u32 v10, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v12, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v11, v0, v7
+; GFX6-NEXT: v_mul_hi_u32 v9, v2, v7
+; GFX6-NEXT: v_mul_lo_u32 v7, v2, v7
+; GFX6-NEXT: v_mul_hi_u32 v8, v2, v5
+; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v5
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
+; GFX6-NEXT: s_add_u32 s0, s10, s14
+; GFX6-NEXT: s_addc_u32 s1, s11, s14
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0
+; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1
+; GFX6-NEXT: v_mul_hi_u32 v7, s11, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0
+; GFX6-NEXT: s_mov_b32 s4, s8
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0
+; GFX6-NEXT: v_mov_b32_e32 v5, s3
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mul_lo_u32 v3, s2, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s11, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s10, v3
+; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
+; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3
+; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
+; GFX6-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
+; GFX6-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
+; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
+; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v6, s11
+; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: s_xor_b64 s[0:1], s[14:15], s[12:13]
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s0, v0
+; GFX6-NEXT: v_xor_b32_e32 v1, s1, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_i64_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x34
+; GFX9-NEXT: s_mov_b32 s3, 0
+; GFX9-NEXT: s_movk_i32 s2, 0x1000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
+; GFX9-NEXT: s_ashr_i32 s8, s3, 31
+; GFX9-NEXT: s_add_u32 s2, s2, s8
+; GFX9-NEXT: s_mov_b32 s9, s8
+; GFX9-NEXT: s_addc_u32 s3, s3, s8
+; GFX9-NEXT: s_xor_b64 s[10:11], s[2:3], s[8:9]
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s10
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s11
+; GFX9-NEXT: s_sub_u32 s12, 0, s10
+; GFX9-NEXT: s_subb_u32 s4, 0, s11
+; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_hi_u32 v4, s12, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s12, v1
+; GFX9-NEXT: v_mul_lo_u32 v6, s4, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s12, v0
+; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v6
+; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v3
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v3
+; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
+; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3]
+; GFX9-NEXT: v_mul_lo_u32 v5, s12, v3
+; GFX9-NEXT: v_mul_hi_u32 v7, s12, v0
+; GFX9-NEXT: v_mul_lo_u32 v8, s4, v0
+; GFX9-NEXT: v_mul_lo_u32 v9, s12, v0
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX9-NEXT: v_add_u32_e32 v5, v7, v5
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v8
+; GFX9-NEXT: v_mul_lo_u32 v10, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v11, v0, v9
+; GFX9-NEXT: v_mul_hi_u32 v12, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v8, v3, v9
+; GFX9-NEXT: v_mul_lo_u32 v9, v3, v9
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v3, v5
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s12, s7, 31
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
+; GFX9-NEXT: s_add_u32 s0, s6, s12
+; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
+; GFX9-NEXT: s_mov_b32 s13, s12
+; GFX9-NEXT: s_addc_u32 s1, s7, s12
+; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[12:13]
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0
+; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1
+; GFX9-NEXT: v_mul_hi_u32 v4, s10, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s11, v0
+; GFX9-NEXT: v_mov_b32_e32 v6, s11
+; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, s10, v0
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
+; GFX9-NEXT: v_sub_u32_e32 v5, s7, v3
+; GFX9-NEXT: v_sub_co_u32_e64 v4, s[0:1], s6, v4
+; GFX9-NEXT: v_subb_co_u32_e64 v5, vcc, v5, v6, s[0:1]
+; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s10, v4
+; GFX9-NEXT: v_subbrev_co_u32_e32 v5, vcc, 0, v5, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 2, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v7, s[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v7, s7
+; GFX9-NEXT: v_subb_co_u32_e64 v3, vcc, v7, v3, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v8, v6, s[2:3]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: s_xor_b64 s[0:1], s[12:13], s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0
+; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX9-NEXT: s_endpgm
%shl.y = shl i64 4096, %y
%r = sdiv i64 %x, %shl.y
store i64 %r, i64 addrspace(1)* %out
@@ -5889,29 +8796,52 @@ define amdgpu_kernel void @sdiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_v2i64_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s8, s1, 31
-; GCN-NEXT: s_lshr_b32 s8, s8, 20
-; GCN-NEXT: s_add_u32 s0, s0, s8
-; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: s_ashr_i32 s8, s3, 31
-; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
-; GCN-NEXT: s_lshr_b32 s8, s8, 20
-; GCN-NEXT: s_add_u32 s2, s2, s8
-; GCN-NEXT: s_addc_u32 s3, s3, 0
-; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: v_mov_b32_e32 v2, s2
-; GCN-NEXT: v_mov_b32_e32 v3, s3
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_v2i64_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s8, s1, 31
+; GFX6-NEXT: s_lshr_b32 s8, s8, 20
+; GFX6-NEXT: s_add_u32 s0, s0, s8
+; GFX6-NEXT: s_addc_u32 s1, s1, 0
+; GFX6-NEXT: s_ashr_i32 s8, s3, 31
+; GFX6-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
+; GFX6-NEXT: s_lshr_b32 s8, s8, 20
+; GFX6-NEXT: s_add_u32 s2, s2, s8
+; GFX6-NEXT: s_addc_u32 s3, s3, 0
+; GFX6-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_v2i64_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s0, s5, 31
+; GFX9-NEXT: s_lshr_b32 s0, s0, 20
+; GFX9-NEXT: s_add_u32 s0, s4, s0
+; GFX9-NEXT: s_addc_u32 s1, s5, 0
+; GFX9-NEXT: s_ashr_i32 s4, s7, 31
+; GFX9-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
+; GFX9-NEXT: s_lshr_b32 s4, s4, 20
+; GFX9-NEXT: s_add_u32 s4, s6, s4
+; GFX9-NEXT: s_addc_u32 s5, s7, 0
+; GFX9-NEXT: s_ashr_i64 s[4:5], s[4:5], 12
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = sdiv <2 x i64> %x, <i64 4096, i64 4096>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void
@@ -5928,132 +8858,258 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)*
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_mov_b32_e32 v0, 0x457ff000
-; GCN-NEXT: v_mov_b32_e32 v1, 0x4f800000
-; GCN-NEXT: v_mac_f32_e32 v0, 0, v1
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_movk_i32 s6, 0xf001
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s0, s9, 31
-; GCN-NEXT: s_lshr_b32 s0, s0, 20
-; GCN-NEXT: v_mul_hi_u32 v2, s6, v0
-; GCN-NEXT: v_mul_lo_u32 v3, v1, s6
-; GCN-NEXT: s_add_u32 s2, s8, s0
-; GCN-NEXT: s_addc_u32 s3, s9, 0
-; GCN-NEXT: s_ashr_i32 s8, s11, 31
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GCN-NEXT: v_mul_lo_u32 v3, v0, s6
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
-; GCN-NEXT: v_mul_lo_u32 v4, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v5, v0, v3
-; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v3
-; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
-; GCN-NEXT: s_mov_b32 s9, s8
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
-; GCN-NEXT: v_mov_b32_e32 v4, 0
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mov_b32_e32 v6, 0
-; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
-; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GCN-NEXT: v_mul_lo_u32 v5, v2, s6
-; GCN-NEXT: v_mul_hi_u32 v7, s6, v0
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
-; GCN-NEXT: v_mul_lo_u32 v7, v0, s6
-; GCN-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5
-; GCN-NEXT: v_mul_lo_u32 v10, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v12, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT: v_mul_hi_u32 v9, v2, v7
-; GCN-NEXT: v_mul_lo_u32 v7, v2, v7
-; GCN-NEXT: v_mul_hi_u32 v8, v2, v5
-; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v2, v5
-; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
-; GCN-NEXT: s_add_u32 s0, s10, s8
-; GCN-NEXT: s_addc_u32 s1, s11, s8
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[8:9]
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, s0, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s0, v0
-; GCN-NEXT: v_mul_hi_u32 v5, s0, v1
-; GCN-NEXT: v_mul_hi_u32 v7, s1, v1
-; GCN-NEXT: v_mul_lo_u32 v1, s1, v1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT: v_mul_lo_u32 v5, s1, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
-; GCN-NEXT: s_movk_i32 s9, 0xfff
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v1, s9
-; GCN-NEXT: v_mul_hi_u32 v3, s9, v0
-; GCN-NEXT: v_mul_lo_u32 v4, v0, s9
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_sub_i32_e32 v4, vcc, s0, v4
-; GCN-NEXT: v_mov_b32_e32 v3, s1
-; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc
-; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s9, v4
-; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
-; GCN-NEXT: s_movk_i32 s0, 0xffe
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3
-; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
-; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
-; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0
-; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
-; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0
-; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4
-; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
-; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GCN-NEXT: v_xor_b32_e32 v0, s8, v0
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0
-; GCN-NEXT: v_xor_b32_e32 v1, s8, v1
-; GCN-NEXT: v_mov_b32_e32 v3, s8
-; GCN-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
-; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: v_mov_b32_e32 v1, s3
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x457ff000
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; GFX6-NEXT: v_mac_f32_e32 v0, 0, v1
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: s_movk_i32 s6, 0xf001
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s0, s9, 31
+; GFX6-NEXT: s_lshr_b32 s0, s0, 20
+; GFX6-NEXT: v_mul_hi_u32 v2, s6, v0
+; GFX6-NEXT: v_mul_lo_u32 v3, v1, s6
+; GFX6-NEXT: s_add_u32 s2, s8, s0
+; GFX6-NEXT: s_addc_u32 s3, s9, 0
+; GFX6-NEXT: s_ashr_i32 s8, s11, 31
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, s6
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3
+; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
+; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT: s_mov_b32 s9, s8
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v6, v4
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mov_b32_e32 v6, 0
+; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
+; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
+; GFX6-NEXT: v_mul_lo_u32 v5, v2, s6
+; GFX6-NEXT: v_mul_hi_u32 v7, s6, v0
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GFX6-NEXT: v_mul_lo_u32 v7, v0, s6
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5
+; GFX6-NEXT: v_mul_lo_u32 v10, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v12, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v11, v0, v7
+; GFX6-NEXT: v_mul_hi_u32 v9, v2, v7
+; GFX6-NEXT: v_mul_lo_u32 v7, v2, v7
+; GFX6-NEXT: v_mul_hi_u32 v8, v2, v5
+; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v5
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
+; GFX6-NEXT: s_add_u32 s0, s10, s8
+; GFX6-NEXT: s_addc_u32 s1, s11, s8
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: s_xor_b64 s[0:1], s[0:1], s[8:9]
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX6-NEXT: v_mul_hi_u32 v5, s0, v1
+; GFX6-NEXT: v_mul_hi_u32 v7, s1, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s1, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT: s_movk_i32 s9, 0xfff
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, s9
+; GFX6-NEXT: v_mul_hi_u32 v3, s9, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, v0, s9
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s0, v4
+; GFX6-NEXT: v_mov_b32_e32 v3, s1
+; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s9, v4
+; GFX6-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
+; GFX6-NEXT: s_movk_i32 s0, 0xffe
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 2, v0
+; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, 1, v0
+; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
+; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0
+; GFX6-NEXT: v_xor_b32_e32 v1, s8, v1
+; GFX6-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_mov_b32_e32 v1, s3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x457ff000
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
+; GFX9-NEXT: v_mac_f32_e32 v0, 0, v1
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_movk_i32 s8, 0xf001
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s2, s5, 31
+; GFX9-NEXT: s_lshr_b32 s2, s2, 20
+; GFX9-NEXT: v_mul_hi_u32 v2, s8, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, s8
+; GFX9-NEXT: v_mul_lo_u32 v5, v0, s8
+; GFX9-NEXT: s_add_u32 s4, s4, s2
+; GFX9-NEXT: s_addc_u32 s5, s5, 0
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
+; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v7, v1, v5
+; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
+; GFX9-NEXT: s_ashr_i64 s[4:5], s[4:5], 12
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX9-NEXT: v_mul_lo_u32 v5, v2, s8
+; GFX9-NEXT: v_mul_hi_u32 v7, s8, v0
+; GFX9-NEXT: v_mul_lo_u32 v8, v0, s8
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24
+; GFX9-NEXT: v_add_u32_e32 v5, v7, v5
+; GFX9-NEXT: v_sub_u32_e32 v5, v5, v0
+; GFX9-NEXT: v_mul_lo_u32 v10, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v11, v0, v8
+; GFX9-NEXT: v_mul_hi_u32 v12, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v9, v2, v8
+; GFX9-NEXT: v_mul_lo_u32 v8, v2, v8
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_mul_hi_u32 v7, v2, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v5
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GFX9-NEXT: s_ashr_i32 s2, s7, 31
+; GFX9-NEXT: s_add_u32 s6, s6, s2
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: s_mov_b32 s3, s2
+; GFX9-NEXT: s_addc_u32 s7, s7, s2
+; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3]
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
+; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX9-NEXT: s_movk_i32 s3, 0xfff
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, v0, s3
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, s3
+; GFX9-NEXT: v_mul_hi_u32 v3, s3, v0
+; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, s6, v5
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
+; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s3, v5
+; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
+; GFX9-NEXT: s_movk_i32 s3, 0xffe
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 2, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 1, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, -1, v5, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v6, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s2, v0
+; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1
+; GFX9-NEXT: v_mov_b32_e32 v3, s2
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
+; GFX9-NEXT: s_endpgm
%r = sdiv <2 x i64> %x, <i64 4096, i64 4095>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void
@@ -6073,275 +9129,544 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: sdiv_v2i64_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11
-; GCN-NEXT: s_mov_b32 s3, 0
-; GCN-NEXT: s_movk_i32 s2, 0x1000
-; GCN-NEXT: s_mov_b32 s18, 0x4f800000
-; GCN-NEXT: s_mov_b32 s19, 0x5f7ffffc
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b64 s[12:13], s[2:3], s6
-; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GCN-NEXT: s_ashr_i32 s16, s3, 31
-; GCN-NEXT: s_add_u32 s2, s2, s16
-; GCN-NEXT: s_mov_b32 s17, s16
-; GCN-NEXT: s_addc_u32 s3, s3, s16
-; GCN-NEXT: s_xor_b64 s[14:15], s[2:3], s[16:17]
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s14
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s15
-; GCN-NEXT: s_mov_b32 s20, 0x2f800000
-; GCN-NEXT: s_mov_b32 s21, 0xcf800000
-; GCN-NEXT: s_sub_u32 s6, 0, s14
-; GCN-NEXT: v_mac_f32_e32 v0, s18, v1
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_subb_u32 s7, 0, s15
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-NEXT: v_mul_f32_e32 v0, s19, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s20, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mac_f32_e32 v0, s21, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s6, v0
-; GCN-NEXT: v_mul_lo_u32 v2, s6, v1
-; GCN-NEXT: v_mul_lo_u32 v4, s7, v0
-; GCN-NEXT: v_mul_lo_u32 v5, s6, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT: v_mul_lo_u32 v3, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v5
-; GCN-NEXT: v_mul_hi_u32 v5, v1, v5
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
-; GCN-NEXT: v_mov_b32_e32 v4, 0
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mov_b32_e32 v6, 0
-; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
-; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
-; GCN-NEXT: v_mul_lo_u32 v5, s6, v2
-; GCN-NEXT: v_mul_hi_u32 v7, s6, v0
-; GCN-NEXT: v_mul_lo_u32 v8, s7, v0
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
-; GCN-NEXT: v_mul_lo_u32 v7, s6, v0
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT: v_mul_lo_u32 v10, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v12, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT: v_mul_hi_u32 v9, v2, v7
-; GCN-NEXT: v_mul_lo_u32 v7, v2, v7
-; GCN-NEXT: v_mul_hi_u32 v8, v2, v5
-; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v2, v5
-; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s2, s9, 31
-; GCN-NEXT: s_add_u32 s0, s8, s2
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: s_mov_b32 s3, s2
-; GCN-NEXT: s_addc_u32 s1, s9, s2
-; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[2:3]
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, s8, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s8, v0
-; GCN-NEXT: v_mul_hi_u32 v5, s8, v1
-; GCN-NEXT: v_mul_hi_u32 v7, s9, v1
-; GCN-NEXT: v_mul_lo_u32 v1, s9, v1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT: v_mul_lo_u32 v5, s9, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s9, v0
-; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17]
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, s14, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s14, v0
-; GCN-NEXT: v_mul_lo_u32 v5, s15, v0
-; GCN-NEXT: v_mov_b32_e32 v7, s15
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mul_lo_u32 v3, s14, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; GCN-NEXT: v_sub_i32_e32 v5, vcc, s9, v2
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, s8, v3
-; GCN-NEXT: v_subb_u32_e64 v5, s[0:1], v5, v7, vcc
-; GCN-NEXT: v_subrev_i32_e64 v7, s[0:1], s14, v3
-; GCN-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v5
-; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v7
-; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s15, v5
-; GCN-NEXT: v_cndmask_b32_e64 v5, v8, v7, s[0:1]
-; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v0
-; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
-; GCN-NEXT: v_add_i32_e64 v9, s[0:1], 1, v0
-; GCN-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1]
-; GCN-NEXT: s_ashr_i32 s8, s13, 31
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
-; GCN-NEXT: s_add_u32 s12, s12, s8
-; GCN-NEXT: v_cndmask_b32_e64 v5, v10, v8, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v8, s9
-; GCN-NEXT: s_mov_b32 s9, s8
-; GCN-NEXT: s_addc_u32 s13, s13, s8
-; GCN-NEXT: s_xor_b64 s[12:13], s[12:13], s[8:9]
-; GCN-NEXT: v_cvt_f32_u32_e32 v10, s12
-; GCN-NEXT: v_cvt_f32_u32_e32 v11, s13
-; GCN-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s15, v2
-; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s14, v3
-; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s15, v2
-; GCN-NEXT: v_mac_f32_e32 v10, s18, v11
-; GCN-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc
-; GCN-NEXT: v_rcp_f32_e32 v3, v10
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GCN-NEXT: s_sub_u32 s14, 0, s12
-; GCN-NEXT: v_mul_f32_e32 v3, s19, v3
-; GCN-NEXT: v_mul_f32_e32 v5, s20, v3
-; GCN-NEXT: v_trunc_f32_e32 v5, v5
-; GCN-NEXT: v_mac_f32_e32 v3, s21, v5
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GCN-NEXT: v_cndmask_b32_e64 v2, v9, v7, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: v_mul_hi_u32 v2, s14, v3
-; GCN-NEXT: v_mul_lo_u32 v7, s14, v5
-; GCN-NEXT: s_subb_u32 s15, 0, s13
-; GCN-NEXT: v_mul_lo_u32 v8, s15, v3
-; GCN-NEXT: v_xor_b32_e32 v0, s2, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; GCN-NEXT: v_mul_lo_u32 v7, s14, v3
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v8
-; GCN-NEXT: v_mul_lo_u32 v8, v3, v2
-; GCN-NEXT: v_mul_hi_u32 v10, v3, v2
-; GCN-NEXT: v_mul_hi_u32 v9, v3, v7
-; GCN-NEXT: v_mul_hi_u32 v11, v5, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v5, v2
-; GCN-NEXT: v_xor_b32_e32 v1, s3, v1
-; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
-; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
-; GCN-NEXT: v_mul_lo_u32 v10, v5, v7
-; GCN-NEXT: v_mul_hi_u32 v7, v5, v7
-; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc
-; GCN-NEXT: v_addc_u32_e32 v8, vcc, v11, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v3, v2
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, v6, v8, vcc
-; GCN-NEXT: v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
-; GCN-NEXT: v_mul_lo_u32 v8, s14, v3
-; GCN-NEXT: v_mul_hi_u32 v9, s14, v2
-; GCN-NEXT: v_mul_lo_u32 v10, s15, v2
-; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
-; GCN-NEXT: v_mul_lo_u32 v9, s14, v2
-; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8
-; GCN-NEXT: v_mul_lo_u32 v12, v2, v8
-; GCN-NEXT: v_mul_hi_u32 v14, v2, v8
-; GCN-NEXT: v_mul_hi_u32 v13, v2, v9
-; GCN-NEXT: v_mul_hi_u32 v11, v3, v9
-; GCN-NEXT: v_mul_lo_u32 v9, v3, v9
-; GCN-NEXT: v_mul_hi_u32 v10, v3, v8
-; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12
-; GCN-NEXT: v_addc_u32_e32 v13, vcc, 0, v14, vcc
-; GCN-NEXT: v_mul_lo_u32 v3, v3, v8
-; GCN-NEXT: v_add_i32_e32 v9, vcc, v12, v9
-; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc
-; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v9, v3
-; GCN-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT: s_ashr_i32 s14, s11, 31
-; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
-; GCN-NEXT: s_add_u32 s0, s10, s14
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GCN-NEXT: s_mov_b32 s15, s14
-; GCN-NEXT: s_addc_u32 s1, s11, s14
-; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT: v_mul_lo_u32 v5, s10, v3
-; GCN-NEXT: v_mul_hi_u32 v7, s10, v2
-; GCN-NEXT: v_mul_hi_u32 v9, s10, v3
-; GCN-NEXT: v_mul_hi_u32 v10, s11, v3
-; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
-; GCN-NEXT: v_mul_lo_u32 v9, s11, v2
-; GCN-NEXT: v_mul_hi_u32 v2, s11, v2
-; GCN-NEXT: v_mov_b32_e32 v8, s3
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v4, s12, v3
-; GCN-NEXT: v_mul_hi_u32 v5, s12, v2
-; GCN-NEXT: v_mul_lo_u32 v6, s13, v2
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_mul_lo_u32 v5, s12, v2
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT: v_sub_i32_e32 v6, vcc, s11, v4
-; GCN-NEXT: v_mov_b32_e32 v7, s13
-; GCN-NEXT: v_sub_i32_e32 v5, vcc, s10, v5
-; GCN-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
-; GCN-NEXT: v_subrev_i32_e64 v7, s[0:1], s12, v5
-; GCN-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v6
-; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v7
-; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v6
-; GCN-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1]
-; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v2
-; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1]
-; GCN-NEXT: v_add_i32_e64 v9, s[0:1], 1, v2
-; GCN-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1]
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
-; GCN-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v8, s11
-; GCN-NEXT: v_subb_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v4
-; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v5
-; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v4
-; GCN-NEXT: v_cndmask_b32_e32 v4, v8, v5, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GCN-NEXT: s_xor_b64 s[0:1], s[14:15], s[8:9]
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; GCN-NEXT: v_xor_b32_e32 v2, s0, v2
-; GCN-NEXT: v_xor_b32_e32 v3, s1, v3
-; GCN-NEXT: v_mov_b32_e32 v4, s1
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s0, v2
-; GCN-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: sdiv_v2i64_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11
+; GFX6-NEXT: s_mov_b32 s3, 0
+; GFX6-NEXT: s_movk_i32 s2, 0x1000
+; GFX6-NEXT: s_mov_b32 s18, 0x4f800000
+; GFX6-NEXT: s_mov_b32 s19, 0x5f7ffffc
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b64 s[12:13], s[2:3], s6
+; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
+; GFX6-NEXT: s_ashr_i32 s16, s3, 31
+; GFX6-NEXT: s_add_u32 s2, s2, s16
+; GFX6-NEXT: s_mov_b32 s17, s16
+; GFX6-NEXT: s_addc_u32 s3, s3, s16
+; GFX6-NEXT: s_xor_b64 s[14:15], s[2:3], s[16:17]
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s14
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s15
+; GFX6-NEXT: s_mov_b32 s20, 0x2f800000
+; GFX6-NEXT: s_mov_b32 s21, 0xcf800000
+; GFX6-NEXT: s_sub_u32 s6, 0, s14
+; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: s_subb_u32 s7, 0, s15
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1
+; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
+; GFX6-NEXT: v_mul_lo_u32 v5, s6, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v4, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
+; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5
+; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mov_b32_e32 v6, 0
+; GFX6-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
+; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT: v_mul_lo_u32 v5, s6, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, s6, v0
+; GFX6-NEXT: v_mul_lo_u32 v8, s7, v0
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GFX6-NEXT: v_mul_lo_u32 v7, s6, v0
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5
+; GFX6-NEXT: v_mul_lo_u32 v10, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v12, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v11, v0, v7
+; GFX6-NEXT: v_mul_hi_u32 v9, v2, v7
+; GFX6-NEXT: v_mul_lo_u32 v7, v2, v7
+; GFX6-NEXT: v_mul_hi_u32 v8, v2, v5
+; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v5
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s2, s9, 31
+; GFX6-NEXT: s_add_u32 s0, s8, s2
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: s_mov_b32 s3, s2
+; GFX6-NEXT: s_addc_u32 s1, s9, s2
+; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[2:3]
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s8, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s8, v0
+; GFX6-NEXT: v_mul_hi_u32 v5, s8, v1
+; GFX6-NEXT: v_mul_hi_u32 v7, s9, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s9, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s9, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0
+; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17]
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s14, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s14, v0
+; GFX6-NEXT: v_mul_lo_u32 v5, s15, v0
+; GFX6-NEXT: v_mov_b32_e32 v7, s15
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mul_lo_u32 v3, s14, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s9, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s8, v3
+; GFX6-NEXT: v_subb_u32_e64 v5, s[0:1], v5, v7, vcc
+; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s14, v3
+; GFX6-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v7
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s15, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v5, v8, v7, s[0:1]
+; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v0
+; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
+; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 1, v0
+; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1]
+; GFX6-NEXT: s_ashr_i32 s8, s13, 31
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
+; GFX6-NEXT: s_add_u32 s12, s12, s8
+; GFX6-NEXT: v_cndmask_b32_e64 v5, v10, v8, s[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v8, s9
+; GFX6-NEXT: s_mov_b32 s9, s8
+; GFX6-NEXT: s_addc_u32 s13, s13, s8
+; GFX6-NEXT: s_xor_b64 s[12:13], s[12:13], s[8:9]
+; GFX6-NEXT: v_cvt_f32_u32_e32 v10, s12
+; GFX6-NEXT: v_cvt_f32_u32_e32 v11, s13
+; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s15, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s15, v2
+; GFX6-NEXT: v_mac_f32_e32 v10, s18, v11
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc
+; GFX6-NEXT: v_rcp_f32_e32 v3, v10
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT: s_sub_u32 s14, 0, s12
+; GFX6-NEXT: v_mul_f32_e32 v3, s19, v3
+; GFX6-NEXT: v_mul_f32_e32 v5, s20, v3
+; GFX6-NEXT: v_trunc_f32_e32 v5, v5
+; GFX6-NEXT: v_mac_f32_e32 v3, s21, v5
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v9, v7, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_mul_hi_u32 v2, s14, v3
+; GFX6-NEXT: v_mul_lo_u32 v7, s14, v5
+; GFX6-NEXT: s_subb_u32 s15, 0, s13
+; GFX6-NEXT: v_mul_lo_u32 v8, s15, v3
+; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v7
+; GFX6-NEXT: v_mul_lo_u32 v7, s14, v3
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v8
+; GFX6-NEXT: v_mul_lo_u32 v8, v3, v2
+; GFX6-NEXT: v_mul_hi_u32 v10, v3, v2
+; GFX6-NEXT: v_mul_hi_u32 v9, v3, v7
+; GFX6-NEXT: v_mul_hi_u32 v11, v5, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v5, v2
+; GFX6-NEXT: v_xor_b32_e32 v1, s3, v1
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
+; GFX6-NEXT: v_mul_lo_u32 v10, v5, v7
+; GFX6-NEXT: v_mul_hi_u32 v7, v5, v7
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
+; GFX6-NEXT: v_add_i32_e64 v2, s[0:1], v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GFX6-NEXT: v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
+; GFX6-NEXT: v_mul_lo_u32 v8, s14, v3
+; GFX6-NEXT: v_mul_hi_u32 v9, s14, v2
+; GFX6-NEXT: v_mul_lo_u32 v10, s15, v2
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GFX6-NEXT: v_mul_lo_u32 v9, s14, v2
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GFX6-NEXT: v_mul_lo_u32 v12, v2, v8
+; GFX6-NEXT: v_mul_hi_u32 v14, v2, v8
+; GFX6-NEXT: v_mul_hi_u32 v13, v2, v9
+; GFX6-NEXT: v_mul_hi_u32 v11, v3, v9
+; GFX6-NEXT: v_mul_lo_u32 v9, v3, v9
+; GFX6-NEXT: v_mul_hi_u32 v10, v3, v8
+; GFX6-NEXT: v_add_i32_e32 v12, vcc, v13, v12
+; GFX6-NEXT: v_addc_u32_e32 v13, vcc, 0, v14, vcc
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, v8
+; GFX6-NEXT: v_add_i32_e32 v9, vcc, v12, v9
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v10, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v9, v3
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GFX6-NEXT: s_ashr_i32 s14, s11, 31
+; GFX6-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
+; GFX6-NEXT: s_add_u32 s0, s10, s14
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT: s_mov_b32 s15, s14
+; GFX6-NEXT: s_addc_u32 s1, s11, s14
+; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s10, v3
+; GFX6-NEXT: v_mul_hi_u32 v7, s10, v2
+; GFX6-NEXT: v_mul_hi_u32 v9, s10, v3
+; GFX6-NEXT: v_mul_hi_u32 v10, s11, v3
+; GFX6-NEXT: v_mul_lo_u32 v3, s11, v3
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
+; GFX6-NEXT: v_mul_lo_u32 v9, s11, v2
+; GFX6-NEXT: v_mul_hi_u32 v2, s11, v2
+; GFX6-NEXT: v_mov_b32_e32 v8, s3
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v9, v5
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v4, s12, v3
+; GFX6-NEXT: v_mul_hi_u32 v5, s12, v2
+; GFX6-NEXT: v_mul_lo_u32 v6, s13, v2
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT: v_mul_lo_u32 v5, s12, v2
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s11, v4
+; GFX6-NEXT: v_mov_b32_e32 v7, s13
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s10, v5
+; GFX6-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
+; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s12, v5
+; GFX6-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v7
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1]
+; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v2
+; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1]
+; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 1, v2
+; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1]
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v8, s11
+; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s13, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v5, vcc
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT: s_xor_b64 s[0:1], s[14:15], s[8:9]
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX6-NEXT: v_xor_b32_e32 v2, s0, v2
+; GFX6-NEXT: v_xor_b32_e32 v3, s1, v3
+; GFX6-NEXT: v_mov_b32_e32 v4, s1
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v2
+; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44
+; GFX9-NEXT: s_mov_b32 s3, 0
+; GFX9-NEXT: s_movk_i32 s2, 0x1000
+; GFX9-NEXT: s_mov_b32 s18, 0x4f800000
+; GFX9-NEXT: s_mov_b32 s19, 0x5f7ffffc
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s6
+; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
+; GFX9-NEXT: s_ashr_i32 s12, s3, 31
+; GFX9-NEXT: s_add_u32 s2, s2, s12
+; GFX9-NEXT: s_mov_b32 s13, s12
+; GFX9-NEXT: s_addc_u32 s3, s3, s12
+; GFX9-NEXT: s_xor_b64 s[10:11], s[2:3], s[12:13]
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s10
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s11
+; GFX9-NEXT: s_mov_b32 s20, 0x2f800000
+; GFX9-NEXT: s_mov_b32 s21, 0xcf800000
+; GFX9-NEXT: s_sub_u32 s14, 0, s10
+; GFX9-NEXT: v_mac_f32_e32 v0, s18, v1
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_subb_u32 s4, 0, s11
+; GFX9-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-NEXT: v_mul_f32_e32 v0, s19, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, s20, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, s21, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s14, v0
+; GFX9-NEXT: v_mul_lo_u32 v2, s14, v1
+; GFX9-NEXT: v_mul_lo_u32 v5, s4, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s14, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX9-NEXT: v_mul_lo_u32 v4, s14, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, s14, v0
+; GFX9-NEXT: v_mul_lo_u32 v8, s4, v0
+; GFX9-NEXT: v_mul_lo_u32 v9, s14, v0
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT: v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v8
+; GFX9-NEXT: v_mul_lo_u32 v10, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v11, v0, v9
+; GFX9-NEXT: v_mul_hi_u32 v12, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v2, v9
+; GFX9-NEXT: v_mul_lo_u32 v9, v2, v9
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_mul_hi_u32 v7, v2, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s14, s5, 31
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX9-NEXT: s_add_u32 s2, s4, s14
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: s_addc_u32 s3, s5, s14
+; GFX9-NEXT: s_mov_b32 s15, s14
+; GFX9-NEXT: s_xor_b64 s[16:17], s[2:3], s[14:15]
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s16, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s16, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s16, v1
+; GFX9-NEXT: v_mul_hi_u32 v7, s17, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s17, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s17, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s17, v0
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; GFX9-NEXT: s_xor_b64 s[12:13], s[14:15], s[12:13]
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s10, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s10, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s11, v0
+; GFX9-NEXT: v_mov_b32_e32 v7, s11
+; GFX9-NEXT: s_ashr_i32 s14, s9, 31
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, s10, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_sub_u32_e32 v4, s17, v2
+; GFX9-NEXT: s_mov_b32 s15, s14
+; GFX9-NEXT: v_sub_co_u32_e64 v3, s[0:1], s16, v3
+; GFX9-NEXT: v_subb_co_u32_e64 v4, vcc, v4, v7, s[0:1]
+; GFX9-NEXT: v_subrev_co_u32_e32 v7, vcc, s10, v3
+; GFX9-NEXT: v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 2, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, 1, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v1, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v10, v8, s[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v8, s17
+; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v8, v2, s[0:1]
+; GFX9-NEXT: s_add_u32 s0, s8, s14
+; GFX9-NEXT: s_addc_u32 s1, s9, s14
+; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[14:15]
+; GFX9-NEXT: v_cvt_f32_u32_e32 v10, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v11, s9
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v2
+; GFX9-NEXT: v_mac_f32_e32 v10, s18, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc
+; GFX9-NEXT: v_rcp_f32_e32 v3, v10
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v9, v7, s[2:3]
+; GFX9-NEXT: v_mul_f32_e32 v3, s19, v3
+; GFX9-NEXT: v_mul_f32_e32 v4, s20, v3
+; GFX9-NEXT: v_trunc_f32_e32 v4, v4
+; GFX9-NEXT: v_mac_f32_e32 v3, s21, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: s_sub_u32 s2, 0, s8
+; GFX9-NEXT: s_subb_u32 s3, 0, s9
+; GFX9-NEXT: v_mul_hi_u32 v7, s2, v3
+; GFX9-NEXT: v_mul_lo_u32 v8, s2, v4
+; GFX9-NEXT: v_mul_lo_u32 v9, s3, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s2, v3
+; GFX9-NEXT: v_add_u32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u32_e32 v7, v7, v9
+; GFX9-NEXT: v_mul_lo_u32 v8, v3, v7
+; GFX9-NEXT: v_mul_hi_u32 v9, v3, v2
+; GFX9-NEXT: v_mul_hi_u32 v10, v3, v7
+; GFX9-NEXT: v_mul_hi_u32 v11, v4, v7
+; GFX9-NEXT: v_mul_lo_u32 v7, v4, v7
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
+; GFX9-NEXT: v_mul_lo_u32 v10, v4, v2
+; GFX9-NEXT: v_mul_hi_u32 v2, v4, v2
+; GFX9-NEXT: s_ashr_i32 s10, s7, 31
+; GFX9-NEXT: s_mov_b32 s11, s10
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v9, v2, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7
+; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v5, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1]
+; GFX9-NEXT: v_mul_lo_u32 v8, s2, v3
+; GFX9-NEXT: v_mul_hi_u32 v9, s2, v2
+; GFX9-NEXT: v_mul_lo_u32 v10, s3, v2
+; GFX9-NEXT: v_mul_lo_u32 v11, s2, v2
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
+; GFX9-NEXT: v_add_u32_e32 v8, v9, v8
+; GFX9-NEXT: v_add_u32_e32 v8, v8, v10
+; GFX9-NEXT: v_mul_lo_u32 v12, v2, v8
+; GFX9-NEXT: v_mul_hi_u32 v13, v2, v11
+; GFX9-NEXT: v_mul_hi_u32 v14, v2, v8
+; GFX9-NEXT: v_mul_hi_u32 v10, v3, v11
+; GFX9-NEXT: v_mul_lo_u32 v11, v3, v11
+; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v13, v12
+; GFX9-NEXT: v_mul_hi_u32 v9, v3, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v14, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v3, v8
+; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v10, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v9, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v10, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v5, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1]
+; GFX9-NEXT: s_add_u32 s0, s6, s10
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
+; GFX9-NEXT: s_addc_u32 s1, s7, s10
+; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11]
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s6, v3
+; GFX9-NEXT: v_mul_hi_u32 v7, s6, v2
+; GFX9-NEXT: v_mul_hi_u32 v9, s6, v3
+; GFX9-NEXT: v_mul_hi_u32 v10, s7, v3
+; GFX9-NEXT: v_mul_lo_u32 v3, s7, v3
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
+; GFX9-NEXT: v_mul_lo_u32 v9, s7, v2
+; GFX9-NEXT: v_mul_hi_u32 v2, s7, v2
+; GFX9-NEXT: v_xor_b32_e32 v0, s12, v0
+; GFX9-NEXT: v_xor_b32_e32 v1, s13, v1
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v9, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v2, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s8, v3
+; GFX9-NEXT: v_mul_hi_u32 v5, s8, v2
+; GFX9-NEXT: v_mul_lo_u32 v7, s9, v2
+; GFX9-NEXT: v_mov_b32_e32 v8, s13
+; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s12, v0
+; GFX9-NEXT: v_add_u32_e32 v4, v5, v4
+; GFX9-NEXT: v_mul_lo_u32 v5, s8, v2
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
+; GFX9-NEXT: v_sub_u32_e32 v7, s7, v4
+; GFX9-NEXT: v_mov_b32_e32 v8, s9
+; GFX9-NEXT: v_sub_co_u32_e64 v5, s[0:1], s6, v5
+; GFX9-NEXT: v_subb_co_u32_e64 v7, vcc, v7, v8, s[0:1]
+; GFX9-NEXT: v_subrev_co_u32_e32 v8, vcc, s8, v5
+; GFX9-NEXT: v_subbrev_co_u32_e32 v7, vcc, 0, v7, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v8, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 2, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 1, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v3, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v9, s7
+; GFX9-NEXT: v_subb_co_u32_e64 v4, vcc, v9, v4, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v5, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v10, v8, s[2:3]
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX9-NEXT: s_xor_b64 s[0:1], s[10:11], s[14:15]
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX9-NEXT: v_xor_b32_e32 v2, s0, v2
+; GFX9-NEXT: v_xor_b32_e32 v3, s1, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s1
+; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v2
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: global_store_dwordx4 v6, v[0:3], s[4:5]
+; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = sdiv <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out
@@ -6354,123 +9679,237 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_i64_oddk_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
-; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_mov_b32 s2, 0xffed2705
-; GCN-NEXT: v_mov_b32_e32 v8, 0
-; GCN-NEXT: v_mov_b32_e32 v7, 0
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
-; GCN-NEXT: v_mul_lo_u32 v2, v1, s2
-; GCN-NEXT: v_mul_lo_u32 v4, v0, s2
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, s8
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
-; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v3, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
-; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
-; GCN-NEXT: s_mov_b32 s5, s9
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GCN-NEXT: v_mul_lo_u32 v4, v2, s2
-; GCN-NEXT: v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_mul_lo_u32 v5, v0, s2
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
-; GCN-NEXT: v_mul_lo_u32 v10, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v12, v0, v4
-; GCN-NEXT: v_mul_hi_u32 v11, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v9, v2, v5
-; GCN-NEXT: v_mul_lo_u32 v5, v2, v5
-; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
-; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT: v_addc_u32_e32 v11, vcc, v8, v12, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v2, v4
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v10, v5
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v11, v9, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: s_ashr_i32 s2, s11, 31
-; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GCN-NEXT: s_add_u32 s0, s10, s2
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: s_mov_b32 s3, s2
-; GCN-NEXT: s_addc_u32 s1, s11, s2
-; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, s0, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s0, v0
-; GCN-NEXT: v_mul_hi_u32 v4, s0, v1
-; GCN-NEXT: v_mul_hi_u32 v5, s1, v1
-; GCN-NEXT: v_mul_lo_u32 v1, s1, v1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v4, s1, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
-; GCN-NEXT: s_mov_b32 s3, 0x12d8fb
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
-; GCN-NEXT: v_mul_hi_u32 v2, s3, v0
-; GCN-NEXT: v_mul_lo_u32 v1, v1, s3
-; GCN-NEXT: v_mul_lo_u32 v0, v0, s3
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
-; GCN-NEXT: v_mov_b32_e32 v2, s1
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s3, v0
-; GCN-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
-; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s3, v2
-; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
-; GCN-NEXT: s_mov_b32 s0, 0x12d8fa
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
-; GCN-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v0
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
-; GCN-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[0:1]
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GCN-NEXT: v_xor_b32_e32 v0, s2, v0
-; GCN-NEXT: v_xor_b32_e32 v1, s2, v1
-; GCN-NEXT: v_mov_b32_e32 v2, s2
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_i64_oddk_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s2, 0xffed2705
+; GFX6-NEXT: v_mov_b32_e32 v8, 0
+; GFX6-NEXT: v_mov_b32_e32 v7, 0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, s2
+; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, s8
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
+; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
+; GFX6-NEXT: s_mov_b32 s5, s9
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
+; GFX6-NEXT: v_mul_lo_u32 v4, v2, s2
+; GFX6-NEXT: v_mul_hi_u32 v5, s2, v0
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, s2
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
+; GFX6-NEXT: v_mul_lo_u32 v10, v0, v4
+; GFX6-NEXT: v_mul_hi_u32 v12, v0, v4
+; GFX6-NEXT: v_mul_hi_u32 v11, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v9, v2, v5
+; GFX6-NEXT: v_mul_lo_u32 v5, v2, v5
+; GFX6-NEXT: v_mul_hi_u32 v6, v2, v4
+; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_addc_u32_e32 v11, vcc, v8, v12, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v10, v5
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v11, v9, vcc
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: s_ashr_i32 s2, s11, 31
+; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
+; GFX6-NEXT: s_add_u32 s0, s10, s2
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: s_mov_b32 s3, s2
+; GFX6-NEXT: s_addc_u32 s1, s11, s2
+; GFX6-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX6-NEXT: v_mul_hi_u32 v4, s0, v1
+; GFX6-NEXT: v_mul_hi_u32 v5, s1, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT: s_mov_b32 s3, 0x12d8fb
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GFX6-NEXT: v_mul_hi_u32 v2, s3, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v0
+; GFX6-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s3, v2
+; GFX6-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
+; GFX6-NEXT: s_mov_b32 s0, 0x12d8fa
+; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[0:1]
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
+; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_i64_oddk_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000
+; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s8, 0xffed2705
+; GFX9-NEXT: v_mov_b32_e32 v7, 0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8
+; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX9-NEXT: v_mul_lo_u32 v4, v2, s8
+; GFX9-NEXT: v_mul_hi_u32 v6, s8, v0
+; GFX9-NEXT: v_mul_lo_u32 v8, v0, s8
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v4, v6, v4
+; GFX9-NEXT: v_sub_u32_e32 v4, v4, v0
+; GFX9-NEXT: v_mul_lo_u32 v10, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v11, v0, v8
+; GFX9-NEXT: v_mul_hi_u32 v12, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v9, v2, v8
+; GFX9-NEXT: v_mul_lo_u32 v8, v2, v8
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_mul_hi_u32 v6, v2, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v7, v12, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s2, s7, 31
+; GFX9-NEXT: s_add_u32 s0, s6, s2
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: s_mov_b32 s3, s2
+; GFX9-NEXT: s_addc_u32 s1, s7, s2
+; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v6, s1, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s1, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s1, v0
+; GFX9-NEXT: s_mov_b32 s3, 0x12d8fb
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
+; GFX9-NEXT: v_mul_hi_u32 v2, s3, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
+; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s3, v0
+; GFX9-NEXT: v_subbrev_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s3, v2
+; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc
+; GFX9-NEXT: s_mov_b32 s3, 0x12d8fa
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
+; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s2, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
+; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5]
+; GFX9-NEXT: s_endpgm
%r = srem i64 %x, 1235195
store i64 %r, i64 addrspace(1)* %out
ret void
@@ -6482,25 +9921,42 @@ define amdgpu_kernel void @srem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x)
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_i64_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s0, s4
-; GCN-NEXT: s_ashr_i32 s4, s7, 31
-; GCN-NEXT: s_lshr_b32 s4, s4, 20
-; GCN-NEXT: s_add_u32 s4, s6, s4
-; GCN-NEXT: s_mov_b32 s1, s5
-; GCN-NEXT: s_addc_u32 s5, s7, 0
-; GCN-NEXT: s_and_b32 s4, s4, 0xfffff000
-; GCN-NEXT: s_sub_u32 s4, s6, s4
-; GCN-NEXT: s_subb_u32 s5, s7, s5
-; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_i64_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_ashr_i32 s4, s7, 31
+; GFX6-NEXT: s_lshr_b32 s4, s4, 20
+; GFX6-NEXT: s_add_u32 s4, s6, s4
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_addc_u32 s5, s7, 0
+; GFX6-NEXT: s_and_b32 s4, s4, 0xfffff000
+; GFX6-NEXT: s_sub_u32 s4, s6, s4
+; GFX6-NEXT: s_subb_u32 s5, s7, s5
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_i64_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s4, s3, 31
+; GFX9-NEXT: s_lshr_b32 s4, s4, 20
+; GFX9-NEXT: s_add_u32 s4, s2, s4
+; GFX9-NEXT: s_addc_u32 s5, s3, 0
+; GFX9-NEXT: s_and_b32 s4, s4, 0xfffff000
+; GFX9-NEXT: s_sub_u32 s2, s2, s4
+; GFX9-NEXT: s_subb_u32 s3, s3, s5
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9-NEXT: s_endpgm
%r = srem i64 %x, 4096
store i64 %r, i64 addrspace(1)* %out
ret void
@@ -6513,144 +9969,280 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_i64_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dword s4, s[0:1], 0xd
-; GCN-NEXT: s_mov_b32 s3, 0
-; GCN-NEXT: s_movk_i32 s2, 0x1000
-; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GCN-NEXT: s_ashr_i32 s4, s3, 31
-; GCN-NEXT: s_add_u32 s2, s2, s4
-; GCN-NEXT: s_mov_b32 s5, s4
-; GCN-NEXT: s_addc_u32 s3, s3, s4
-; GCN-NEXT: s_xor_b64 s[12:13], s[2:3], s[4:5]
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13
-; GCN-NEXT: s_sub_u32 s2, 0, s12
-; GCN-NEXT: s_subb_u32 s3, 0, s13
-; GCN-NEXT: s_ashr_i32 s14, s11, 31
-; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_mov_b32 s15, s14
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_mov_b32 s4, s8
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_mov_b32 s5, s9
-; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
-; GCN-NEXT: v_mul_lo_u32 v2, s2, v1
-; GCN-NEXT: v_mul_lo_u32 v5, s3, v0
-; GCN-NEXT: v_mul_lo_u32 v4, s2, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; GCN-NEXT: v_mul_hi_u32 v3, v0, v4
-; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
-; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GCN-NEXT: v_mov_b32_e32 v4, 0
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mov_b32_e32 v6, 0
-; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
-; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GCN-NEXT: v_mul_lo_u32 v5, s2, v2
-; GCN-NEXT: v_mul_hi_u32 v7, s2, v0
-; GCN-NEXT: v_mul_lo_u32 v8, s3, v0
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
-; GCN-NEXT: v_mul_lo_u32 v7, s2, v0
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT: v_mul_lo_u32 v10, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v12, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT: v_mul_hi_u32 v9, v2, v7
-; GCN-NEXT: v_mul_lo_u32 v7, v2, v7
-; GCN-NEXT: v_mul_hi_u32 v8, v2, v5
-; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v2, v5
-; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
-; GCN-NEXT: s_add_u32 s0, s10, s14
-; GCN-NEXT: s_addc_u32 s1, s11, s14
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, s10, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s10, v0
-; GCN-NEXT: v_mul_hi_u32 v5, s10, v1
-; GCN-NEXT: v_mul_hi_u32 v7, s11, v1
-; GCN-NEXT: v_mul_lo_u32 v1, s11, v1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT: v_mul_lo_u32 v5, s11, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GCN-NEXT: v_mul_lo_u32 v1, s12, v1
-; GCN-NEXT: v_mul_hi_u32 v2, s12, v0
-; GCN-NEXT: v_mul_lo_u32 v3, s13, v0
-; GCN-NEXT: v_mul_lo_u32 v0, s12, v0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s11, v1
-; GCN-NEXT: v_mov_b32_e32 v3, s13
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s10, v0
-; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
-; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0
-; GCN-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
-; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v5
-; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3]
-; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v4
-; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s12, v4
-; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v5
-; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3]
-; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
-; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v5, s11
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
-; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
-; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1
-; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: v_xor_b32_e32 v0, s14, v0
-; GCN-NEXT: v_xor_b32_e32 v1, s14, v1
-; GCN-NEXT: v_mov_b32_e32 v2, s14
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s14, v0
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_i64_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dword s4, s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s3, 0
+; GFX6-NEXT: s_movk_i32 s2, 0x1000
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
+; GFX6-NEXT: s_ashr_i32 s4, s3, 31
+; GFX6-NEXT: s_add_u32 s2, s2, s4
+; GFX6-NEXT: s_mov_b32 s5, s4
+; GFX6-NEXT: s_addc_u32 s3, s3, s4
+; GFX6-NEXT: s_xor_b64 s[12:13], s[2:3], s[4:5]
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13
+; GFX6-NEXT: s_sub_u32 s2, 0, s12
+; GFX6-NEXT: s_subb_u32 s3, 0, s13
+; GFX6-NEXT: s_ashr_i32 s14, s11, 31
+; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s15, s14
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s4, s8
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_mov_b32 s5, s9
+; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
+; GFX6-NEXT: v_mul_lo_u32 v5, s3, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s2, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
+; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mov_b32_e32 v6, 0
+; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
+; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
+; GFX6-NEXT: v_mul_lo_u32 v5, s2, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, s2, v0
+; GFX6-NEXT: v_mul_lo_u32 v8, s3, v0
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GFX6-NEXT: v_mul_lo_u32 v7, s2, v0
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5
+; GFX6-NEXT: v_mul_lo_u32 v10, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v12, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v11, v0, v7
+; GFX6-NEXT: v_mul_hi_u32 v9, v2, v7
+; GFX6-NEXT: v_mul_lo_u32 v7, v2, v7
+; GFX6-NEXT: v_mul_hi_u32 v8, v2, v5
+; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v5
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
+; GFX6-NEXT: s_add_u32 s0, s10, s14
+; GFX6-NEXT: s_addc_u32 s1, s11, s14
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0
+; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1
+; GFX6-NEXT: v_mul_hi_u32 v7, s11, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, s12, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, s12, v0
+; GFX6-NEXT: v_mul_lo_u32 v3, s13, v0
+; GFX6-NEXT: v_mul_lo_u32 v0, s12, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s11, v1
+; GFX6-NEXT: v_mov_b32_e32 v3, s13
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s10, v0
+; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
+; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0
+; GFX6-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v5
+; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v4
+; GFX6-NEXT: v_subrev_i32_e64 v3, s[0:1], s12, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3]
+; GFX6-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v5, s11
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
+; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s14, v0
+; GFX6-NEXT: v_xor_b32_e32 v1, s14, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s14, v0
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_i64_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s4, s[0:1], 0x34
+; GFX9-NEXT: s_mov_b32 s3, 0
+; GFX9-NEXT: s_movk_i32 s2, 0x1000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
+; GFX9-NEXT: s_ashr_i32 s4, s3, 31
+; GFX9-NEXT: s_add_u32 s2, s2, s4
+; GFX9-NEXT: s_mov_b32 s5, s4
+; GFX9-NEXT: s_addc_u32 s3, s3, s4
+; GFX9-NEXT: s_xor_b64 s[8:9], s[2:3], s[4:5]
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
+; GFX9-NEXT: s_sub_u32 s10, 0, s8
+; GFX9-NEXT: s_subb_u32 s4, 0, s9
+; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_hi_u32 v4, s10, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1
+; GFX9-NEXT: v_mul_lo_u32 v6, s4, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s10, v0
+; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v6
+; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v3
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v3
+; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
+; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3]
+; GFX9-NEXT: v_mul_lo_u32 v5, s10, v3
+; GFX9-NEXT: v_mul_hi_u32 v7, s10, v0
+; GFX9-NEXT: v_mul_lo_u32 v8, s4, v0
+; GFX9-NEXT: v_mul_lo_u32 v9, s10, v0
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX9-NEXT: v_add_u32_e32 v5, v7, v5
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v8
+; GFX9-NEXT: v_mul_lo_u32 v10, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v11, v0, v9
+; GFX9-NEXT: v_mul_hi_u32 v12, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v8, v3, v9
+; GFX9-NEXT: v_mul_lo_u32 v9, v3, v9
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v3, v5
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s10, s7, 31
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
+; GFX9-NEXT: s_add_u32 s0, s6, s10
+; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
+; GFX9-NEXT: s_mov_b32 s11, s10
+; GFX9-NEXT: s_addc_u32 s1, s7, s10
+; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11]
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0
+; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v1, s8, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s9, v0
+; GFX9-NEXT: v_mul_lo_u32 v0, s8, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v3, v1
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
+; GFX9-NEXT: v_sub_co_u32_e64 v0, s[0:1], s6, v0
+; GFX9-NEXT: v_sub_u32_e32 v3, s7, v1
+; GFX9-NEXT: v_mov_b32_e32 v4, s9
+; GFX9-NEXT: v_subb_co_u32_e64 v3, vcc, v3, v4, s[0:1]
+; GFX9-NEXT: v_subrev_co_u32_e64 v5, s[2:3], s8, v0
+; GFX9-NEXT: v_subbrev_co_u32_e64 v6, vcc, 0, v3, s[2:3]
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX9-NEXT: v_subb_co_u32_e64 v3, vcc, v3, v4, s[2:3]
+; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s8, v5
+; GFX9-NEXT: v_subbrev_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v6, s7
+; GFX9-NEXT: v_subb_co_u32_e64 v1, vcc, v6, v1, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[2:3]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s10, v0
+; GFX9-NEXT: v_xor_b32_e32 v1, s10, v1
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
+; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s10, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
+; GFX9-NEXT: s_endpgm
%shl.y = shl i64 4096, %y
%r = srem i64 %x, %shl.y
store i64 %r, i64 addrspace(1)* %out
@@ -6668,34 +10260,62 @@ define amdgpu_kernel void @srem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out,
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_v2i64_pow2k_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
-; GCN-NEXT: s_movk_i32 s8, 0xf000
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s9, s1, 31
-; GCN-NEXT: s_lshr_b32 s9, s9, 20
-; GCN-NEXT: s_add_u32 s9, s0, s9
-; GCN-NEXT: s_addc_u32 s10, s1, 0
-; GCN-NEXT: s_and_b32 s9, s9, s8
-; GCN-NEXT: s_sub_u32 s0, s0, s9
-; GCN-NEXT: s_subb_u32 s1, s1, s10
-; GCN-NEXT: s_ashr_i32 s9, s3, 31
-; GCN-NEXT: s_lshr_b32 s9, s9, 20
-; GCN-NEXT: s_add_u32 s9, s2, s9
-; GCN-NEXT: s_addc_u32 s10, s3, 0
-; GCN-NEXT: s_and_b32 s8, s9, s8
-; GCN-NEXT: s_sub_u32 s2, s2, s8
-; GCN-NEXT: s_subb_u32 s3, s3, s10
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: v_mov_b32_e32 v2, s2
-; GCN-NEXT: v_mov_b32_e32 v3, s3
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_v2i64_pow2k_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX6-NEXT: s_movk_i32 s8, 0xf000
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s9, s1, 31
+; GFX6-NEXT: s_lshr_b32 s9, s9, 20
+; GFX6-NEXT: s_add_u32 s9, s0, s9
+; GFX6-NEXT: s_addc_u32 s10, s1, 0
+; GFX6-NEXT: s_and_b32 s9, s9, s8
+; GFX6-NEXT: s_sub_u32 s0, s0, s9
+; GFX6-NEXT: s_subb_u32 s1, s1, s10
+; GFX6-NEXT: s_ashr_i32 s9, s3, 31
+; GFX6-NEXT: s_lshr_b32 s9, s9, 20
+; GFX6-NEXT: s_add_u32 s9, s2, s9
+; GFX6-NEXT: s_addc_u32 s10, s3, 0
+; GFX6-NEXT: s_and_b32 s8, s9, s8
+; GFX6-NEXT: s_sub_u32 s2, s2, s8
+; GFX6-NEXT: s_subb_u32 s3, s3, s10
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_v2i64_pow2k_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
+; GFX9-NEXT: s_movk_i32 s8, 0xf000
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s0, s5, 31
+; GFX9-NEXT: s_lshr_b32 s0, s0, 20
+; GFX9-NEXT: s_add_u32 s0, s4, s0
+; GFX9-NEXT: s_addc_u32 s1, s5, 0
+; GFX9-NEXT: s_and_b32 s0, s0, s8
+; GFX9-NEXT: s_sub_u32 s0, s4, s0
+; GFX9-NEXT: s_subb_u32 s1, s5, s1
+; GFX9-NEXT: s_ashr_i32 s4, s7, 31
+; GFX9-NEXT: s_lshr_b32 s4, s4, 20
+; GFX9-NEXT: s_add_u32 s4, s6, s4
+; GFX9-NEXT: s_addc_u32 s5, s7, 0
+; GFX9-NEXT: s_and_b32 s4, s4, s8
+; GFX9-NEXT: s_sub_u32 s4, s6, s4
+; GFX9-NEXT: s_subb_u32 s5, s7, s5
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX9-NEXT: s_endpgm
%r = srem <2 x i64> %x, <i64 4096, i64 4096>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void
@@ -6715,271 +10335,536 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou
; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void
;
-; GCN-LABEL: srem_v2i64_pow2_shl_denom:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11
-; GCN-NEXT: s_mov_b32 s3, 0
-; GCN-NEXT: s_movk_i32 s2, 0x1000
-; GCN-NEXT: s_mov_b32 s18, 0x4f800000
-; GCN-NEXT: s_mov_b32 s19, 0x5f7ffffc
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshl_b64 s[14:15], s[2:3], s6
-; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
-; GCN-NEXT: s_ashr_i32 s4, s3, 31
-; GCN-NEXT: s_add_u32 s2, s2, s4
-; GCN-NEXT: s_mov_b32 s5, s4
-; GCN-NEXT: s_addc_u32 s3, s3, s4
-; GCN-NEXT: s_xor_b64 s[16:17], s[2:3], s[4:5]
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s16
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s17
-; GCN-NEXT: s_mov_b32 s20, 0x2f800000
-; GCN-NEXT: s_mov_b32 s21, 0xcf800000
-; GCN-NEXT: s_sub_u32 s6, 0, s16
-; GCN-NEXT: v_mac_f32_e32 v0, s18, v1
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: s_subb_u32 s7, 0, s17
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-NEXT: v_mul_f32_e32 v0, s19, v0
-; GCN-NEXT: v_mul_f32_e32 v1, s20, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mac_f32_e32 v0, s21, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i32 s12, s9, 31
-; GCN-NEXT: s_add_u32 s0, s8, s12
-; GCN-NEXT: v_mul_hi_u32 v3, s6, v0
-; GCN-NEXT: v_mul_lo_u32 v2, s6, v1
-; GCN-NEXT: v_mul_lo_u32 v4, s7, v0
-; GCN-NEXT: v_mul_lo_u32 v5, s6, v0
-; GCN-NEXT: s_mov_b32 s13, s12
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT: v_mul_lo_u32 v3, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
-; GCN-NEXT: v_mul_lo_u32 v6, v1, v5
-; GCN-NEXT: v_mul_hi_u32 v5, v1, v5
-; GCN-NEXT: s_addc_u32 s1, s9, s12
-; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13]
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
-; GCN-NEXT: v_mov_b32_e32 v4, 0
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_mov_b32_e32 v6, 0
-; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
-; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
-; GCN-NEXT: v_mul_lo_u32 v5, s6, v2
-; GCN-NEXT: v_mul_hi_u32 v7, s6, v0
-; GCN-NEXT: v_mul_lo_u32 v8, s7, v0
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
-; GCN-NEXT: v_mul_lo_u32 v7, s6, v0
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT: v_mul_lo_u32 v10, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v12, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT: v_mul_hi_u32 v9, v2, v7
-; GCN-NEXT: v_mul_lo_u32 v7, v2, v7
-; GCN-NEXT: v_mul_hi_u32 v8, v2, v5
-; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v2, v5
-; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, s8, v1
-; GCN-NEXT: v_mul_hi_u32 v3, s8, v0
-; GCN-NEXT: v_mul_hi_u32 v5, s8, v1
-; GCN-NEXT: v_mul_hi_u32 v7, s9, v1
-; GCN-NEXT: v_mul_lo_u32 v1, s9, v1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT: v_mul_lo_u32 v5, s9, v0
-; GCN-NEXT: v_mul_hi_u32 v0, s9, v0
-; GCN-NEXT: s_mov_b32 s6, -1
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GCN-NEXT: v_mul_lo_u32 v1, s16, v1
-; GCN-NEXT: v_mul_hi_u32 v2, s16, v0
-; GCN-NEXT: v_mul_lo_u32 v3, s17, v0
-; GCN-NEXT: v_mul_lo_u32 v0, s16, v0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s9, v1
-; GCN-NEXT: v_mov_b32_e32 v3, s17
-; GCN-NEXT: v_sub_i32_e32 v0, vcc, s8, v0
-; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
-; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s16, v0
-; GCN-NEXT: v_subbrev_u32_e64 v7, s[2:3], 0, v2, s[0:1]
-; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s17, v7
-; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
-; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s16, v5
-; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s16, v5
-; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s17, v7
-; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3]
-; GCN-NEXT: s_ashr_i32 s2, s15, 31
-; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8
-; GCN-NEXT: s_add_u32 s8, s14, s2
-; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v2, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v7, s9
-; GCN-NEXT: s_mov_b32 s3, s2
-; GCN-NEXT: s_addc_u32 s9, s15, s2
-; GCN-NEXT: s_xor_b64 s[8:9], s[8:9], s[2:3]
-; GCN-NEXT: v_cvt_f32_u32_e32 v8, s8
-; GCN-NEXT: v_cvt_f32_u32_e32 v9, s9
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v7, v1, vcc
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s17, v1
-; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
-; GCN-NEXT: v_mac_f32_e32 v8, s18, v9
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s16, v0
-; GCN-NEXT: v_rcp_f32_e32 v8, v8
-; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s17, v1
-; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v3, s[0:1]
-; GCN-NEXT: v_mul_f32_e32 v3, s19, v8
-; GCN-NEXT: v_mul_f32_e32 v5, s20, v3
-; GCN-NEXT: v_trunc_f32_e32 v5, v5
-; GCN-NEXT: v_mac_f32_e32 v3, s21, v5
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GCN-NEXT: s_sub_u32 s2, 0, s8
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT: v_mul_hi_u32 v2, s2, v3
-; GCN-NEXT: v_mul_lo_u32 v7, s2, v5
-; GCN-NEXT: s_subb_u32 s3, 0, s9
-; GCN-NEXT: v_mul_lo_u32 v8, s3, v3
-; GCN-NEXT: s_ashr_i32 s14, s11, 31
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; GCN-NEXT: v_mul_lo_u32 v7, s2, v3
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v8
-; GCN-NEXT: v_mul_lo_u32 v8, v3, v2
-; GCN-NEXT: v_mul_hi_u32 v10, v3, v2
-; GCN-NEXT: v_mul_hi_u32 v9, v3, v7
-; GCN-NEXT: v_mul_hi_u32 v11, v5, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v5, v2
-; GCN-NEXT: s_mov_b32 s15, s14
-; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
-; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
-; GCN-NEXT: v_mul_lo_u32 v10, v5, v7
-; GCN-NEXT: v_mul_hi_u32 v7, v5, v7
-; GCN-NEXT: v_xor_b32_e32 v0, s12, v0
-; GCN-NEXT: v_xor_b32_e32 v1, s12, v1
-; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc
-; GCN-NEXT: v_addc_u32_e32 v8, vcc, v11, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v3, v2
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, v6, v8, vcc
-; GCN-NEXT: v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
-; GCN-NEXT: v_mul_lo_u32 v8, s2, v3
-; GCN-NEXT: v_mul_hi_u32 v9, s2, v2
-; GCN-NEXT: v_mul_lo_u32 v10, s3, v2
-; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
-; GCN-NEXT: v_mul_lo_u32 v9, s2, v2
-; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8
-; GCN-NEXT: v_mul_lo_u32 v12, v2, v8
-; GCN-NEXT: v_mul_hi_u32 v14, v2, v8
-; GCN-NEXT: v_mul_hi_u32 v13, v2, v9
-; GCN-NEXT: v_mul_hi_u32 v11, v3, v9
-; GCN-NEXT: v_mul_lo_u32 v9, v3, v9
-; GCN-NEXT: v_mul_hi_u32 v10, v3, v8
-; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12
-; GCN-NEXT: v_addc_u32_e32 v13, vcc, 0, v14, vcc
-; GCN-NEXT: v_mul_lo_u32 v3, v3, v8
-; GCN-NEXT: v_add_i32_e32 v9, vcc, v12, v9
-; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc
-; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v9, v3
-; GCN-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
-; GCN-NEXT: s_add_u32 s0, s10, s14
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GCN-NEXT: s_addc_u32 s1, s11, s14
-; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GCN-NEXT: v_mul_lo_u32 v5, s10, v3
-; GCN-NEXT: v_mul_hi_u32 v7, s10, v2
-; GCN-NEXT: v_mul_hi_u32 v9, s10, v3
-; GCN-NEXT: v_mul_hi_u32 v10, s11, v3
-; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
-; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
-; GCN-NEXT: v_mul_lo_u32 v9, s11, v2
-; GCN-NEXT: v_mul_hi_u32 v2, s11, v2
-; GCN-NEXT: v_mov_b32_e32 v8, s12
-; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v3, s8, v3
-; GCN-NEXT: v_mul_hi_u32 v4, s8, v2
-; GCN-NEXT: v_mul_lo_u32 v5, s9, v2
-; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0
-; GCN-NEXT: v_mul_lo_u32 v2, s8, v2
-; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v3
-; GCN-NEXT: v_mov_b32_e32 v5, s9
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, s10, v2
-; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s8, v2
-; GCN-NEXT: v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1]
-; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s9, v7
-; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
-; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s8, v6
-; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v6
-; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3]
-; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s9, v7
-; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3]
-; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8
-; GCN-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v7, s11
-; GCN-NEXT: v_subb_u32_e32 v3, vcc, v7, v3, vcc
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
-; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
-; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3
-; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GCN-NEXT: v_xor_b32_e32 v2, s14, v2
-; GCN-NEXT: v_xor_b32_e32 v3, s14, v3
-; GCN-NEXT: v_mov_b32_e32 v4, s14
-; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s14, v2
-; GCN-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; GCN-NEXT: s_endpgm
+; GFX6-LABEL: srem_v2i64_pow2_shl_denom:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11
+; GFX6-NEXT: s_mov_b32 s3, 0
+; GFX6-NEXT: s_movk_i32 s2, 0x1000
+; GFX6-NEXT: s_mov_b32 s18, 0x4f800000
+; GFX6-NEXT: s_mov_b32 s19, 0x5f7ffffc
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b64 s[14:15], s[2:3], s6
+; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
+; GFX6-NEXT: s_ashr_i32 s4, s3, 31
+; GFX6-NEXT: s_add_u32 s2, s2, s4
+; GFX6-NEXT: s_mov_b32 s5, s4
+; GFX6-NEXT: s_addc_u32 s3, s3, s4
+; GFX6-NEXT: s_xor_b64 s[16:17], s[2:3], s[4:5]
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s16
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s17
+; GFX6-NEXT: s_mov_b32 s20, 0x2f800000
+; GFX6-NEXT: s_mov_b32 s21, 0xcf800000
+; GFX6-NEXT: s_sub_u32 s6, 0, s16
+; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1
+; GFX6-NEXT: v_rcp_f32_e32 v0, v0
+; GFX6-NEXT: s_subb_u32 s7, 0, s17
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_ashr_i32 s12, s9, 31
+; GFX6-NEXT: s_add_u32 s0, s8, s12
+; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1
+; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
+; GFX6-NEXT: v_mul_lo_u32 v5, s6, v0
+; GFX6-NEXT: s_mov_b32 s13, s12
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v4, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
+; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5
+; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5
+; GFX6-NEXT: s_addc_u32 s1, s9, s12
+; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13]
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, 0
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mov_b32_e32 v6, 0
+; GFX6-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
+; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT: v_mul_lo_u32 v5, s6, v2
+; GFX6-NEXT: v_mul_hi_u32 v7, s6, v0
+; GFX6-NEXT: v_mul_lo_u32 v8, s7, v0
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GFX6-NEXT: v_mul_lo_u32 v7, s6, v0
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5
+; GFX6-NEXT: v_mul_lo_u32 v10, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v12, v0, v5
+; GFX6-NEXT: v_mul_hi_u32 v11, v0, v7
+; GFX6-NEXT: v_mul_hi_u32 v9, v2, v7
+; GFX6-NEXT: v_mul_lo_u32 v7, v2, v7
+; GFX6-NEXT: v_mul_hi_u32 v8, v2, v5
+; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v5
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
+; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, s8, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, s8, v0
+; GFX6-NEXT: v_mul_hi_u32 v5, s8, v1
+; GFX6-NEXT: v_mul_hi_u32 v7, s9, v1
+; GFX6-NEXT: v_mul_lo_u32 v1, s9, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s9, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, s16, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, s16, v0
+; GFX6-NEXT: v_mul_lo_u32 v3, s17, v0
+; GFX6-NEXT: v_mul_lo_u32 v0, s16, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s9, v1
+; GFX6-NEXT: v_mov_b32_e32 v3, s17
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
+; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s16, v0
+; GFX6-NEXT: v_subbrev_u32_e64 v7, s[2:3], 0, v2, s[0:1]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s17, v7
+; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s16, v5
+; GFX6-NEXT: v_subrev_i32_e64 v3, s[0:1], s16, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s17, v7
+; GFX6-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3]
+; GFX6-NEXT: s_ashr_i32 s2, s15, 31
+; GFX6-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8
+; GFX6-NEXT: s_add_u32 s8, s14, s2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, v2, s[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v7, s9
+; GFX6-NEXT: s_mov_b32 s3, s2
+; GFX6-NEXT: s_addc_u32 s9, s15, s2
+; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[2:3]
+; GFX6-NEXT: v_cvt_f32_u32_e32 v8, s8
+; GFX6-NEXT: v_cvt_f32_u32_e32 v9, s9
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v7, v1, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s17, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX6-NEXT: v_mac_f32_e32 v8, s18, v9
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s16, v0
+; GFX6-NEXT: v_rcp_f32_e32 v8, v8
+; GFX6-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s17, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v3, s[0:1]
+; GFX6-NEXT: v_mul_f32_e32 v3, s19, v8
+; GFX6-NEXT: v_mul_f32_e32 v5, s20, v3
+; GFX6-NEXT: v_trunc_f32_e32 v5, v5
+; GFX6-NEXT: v_mac_f32_e32 v3, s21, v5
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX6-NEXT: s_sub_u32 s2, 0, s8
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_mul_hi_u32 v2, s2, v3
+; GFX6-NEXT: v_mul_lo_u32 v7, s2, v5
+; GFX6-NEXT: s_subb_u32 s3, 0, s9
+; GFX6-NEXT: v_mul_lo_u32 v8, s3, v3
+; GFX6-NEXT: s_ashr_i32 s14, s11, 31
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v7
+; GFX6-NEXT: v_mul_lo_u32 v7, s2, v3
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v8
+; GFX6-NEXT: v_mul_lo_u32 v8, v3, v2
+; GFX6-NEXT: v_mul_hi_u32 v10, v3, v2
+; GFX6-NEXT: v_mul_hi_u32 v9, v3, v7
+; GFX6-NEXT: v_mul_hi_u32 v11, v5, v2
+; GFX6-NEXT: v_mul_lo_u32 v2, v5, v2
+; GFX6-NEXT: s_mov_b32 s15, s14
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
+; GFX6-NEXT: v_mul_lo_u32 v10, v5, v7
+; GFX6-NEXT: v_mul_hi_u32 v7, v5, v7
+; GFX6-NEXT: v_xor_b32_e32 v0, s12, v0
+; GFX6-NEXT: v_xor_b32_e32 v1, s12, v1
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
+; GFX6-NEXT: v_add_i32_e64 v2, s[0:1], v3, v2
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GFX6-NEXT: v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
+; GFX6-NEXT: v_mul_lo_u32 v8, s2, v3
+; GFX6-NEXT: v_mul_hi_u32 v9, s2, v2
+; GFX6-NEXT: v_mul_lo_u32 v10, s3, v2
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; GFX6-NEXT: v_mul_lo_u32 v9, s2, v2
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GFX6-NEXT: v_mul_lo_u32 v12, v2, v8
+; GFX6-NEXT: v_mul_hi_u32 v14, v2, v8
+; GFX6-NEXT: v_mul_hi_u32 v13, v2, v9
+; GFX6-NEXT: v_mul_hi_u32 v11, v3, v9
+; GFX6-NEXT: v_mul_lo_u32 v9, v3, v9
+; GFX6-NEXT: v_mul_hi_u32 v10, v3, v8
+; GFX6-NEXT: v_add_i32_e32 v12, vcc, v13, v12
+; GFX6-NEXT: v_addc_u32_e32 v13, vcc, 0, v14, vcc
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, v8
+; GFX6-NEXT: v_add_i32_e32 v9, vcc, v12, v9
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v10, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v9, v3
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v7
+; GFX6-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
+; GFX6-NEXT: s_add_u32 s0, s10, s14
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT: s_addc_u32 s1, s11, s14
+; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s10, v3
+; GFX6-NEXT: v_mul_hi_u32 v7, s10, v2
+; GFX6-NEXT: v_mul_hi_u32 v9, s10, v3
+; GFX6-NEXT: v_mul_hi_u32 v10, s11, v3
+; GFX6-NEXT: v_mul_lo_u32 v3, s11, v3
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
+; GFX6-NEXT: v_mul_lo_u32 v9, s11, v2
+; GFX6-NEXT: v_mul_hi_u32 v2, s11, v2
+; GFX6-NEXT: v_mov_b32_e32 v8, s12
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v9, v5
+; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v3, s8, v3
+; GFX6-NEXT: v_mul_hi_u32 v4, s8, v2
+; GFX6-NEXT: v_mul_lo_u32 v5, s9, v2
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, s8, v2
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s11, v3
+; GFX6-NEXT: v_mov_b32_e32 v5, s9
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s10, v2
+; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
+; GFX6-NEXT: v_subrev_i32_e64 v6, s[0:1], s8, v2
+; GFX6-NEXT: v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s9, v7
+; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
+; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s8, v6
+; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s9, v7
+; GFX6-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3]
+; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
+; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v7, s11
+; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v7, v3, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
+; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT: v_xor_b32_e32 v2, s14, v2
+; GFX6-NEXT: v_xor_b32_e32 v3, s14, v3
+; GFX6-NEXT: v_mov_b32_e32 v4, s14
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s14, v2
+; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: srem_v2i64_pow2_shl_denom:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x44
+; GFX9-NEXT: s_mov_b32 s3, 0
+; GFX9-NEXT: s_movk_i32 s2, 0x1000
+; GFX9-NEXT: s_mov_b32 s16, 0x4f800000
+; GFX9-NEXT: s_mov_b32 s17, 0x5f7ffffc
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b64 s[12:13], s[2:3], s6
+; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
+; GFX9-NEXT: s_ashr_i32 s4, s3, 31
+; GFX9-NEXT: s_add_u32 s2, s2, s4
+; GFX9-NEXT: s_mov_b32 s5, s4
+; GFX9-NEXT: s_addc_u32 s3, s3, s4
+; GFX9-NEXT: s_xor_b64 s[14:15], s[2:3], s[4:5]
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s14
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s15
+; GFX9-NEXT: s_mov_b32 s18, 0x2f800000
+; GFX9-NEXT: s_mov_b32 s19, 0xcf800000
+; GFX9-NEXT: s_sub_u32 s4, 0, s14
+; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_subb_u32 s5, 0, s15
+; GFX9-NEXT: v_mov_b32_e32 v6, 0
+; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34
+; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_ashr_i32 s6, s9, 31
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: v_mul_hi_u32 v3, s4, v0
+; GFX9-NEXT: v_mul_lo_u32 v2, s4, v1
+; GFX9-NEXT: v_mul_lo_u32 v5, s5, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s4, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX9-NEXT: v_mul_lo_u32 v4, s4, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, s4, v0
+; GFX9-NEXT: v_mul_lo_u32 v8, s5, v0
+; GFX9-NEXT: v_mul_lo_u32 v9, s4, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v8
+; GFX9-NEXT: v_mul_lo_u32 v10, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v11, v0, v9
+; GFX9-NEXT: v_mul_hi_u32 v12, v0, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v2, v9
+; GFX9-NEXT: v_mul_lo_u32 v9, v2, v9
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT: v_mul_hi_u32 v7, v2, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX9-NEXT: s_add_u32 s2, s8, s6
+; GFX9-NEXT: s_addc_u32 s3, s9, s6
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: s_xor_b64 s[8:9], s[2:3], s[6:7]
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s8, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s8, v1
+; GFX9-NEXT: v_mul_hi_u32 v7, s9, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s9, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s9, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v1, s14, v1
+; GFX9-NEXT: v_mul_hi_u32 v2, s14, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s15, v0
+; GFX9-NEXT: v_mul_lo_u32 v0, s14, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_sub_co_u32_e64 v0, s[0:1], s8, v0
+; GFX9-NEXT: v_sub_u32_e32 v2, s9, v1
+; GFX9-NEXT: v_mov_b32_e32 v3, s15
+; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v2, v3, s[0:1]
+; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[2:3], s14, v0
+; GFX9-NEXT: v_subbrev_co_u32_e64 v7, vcc, 0, v2, s[2:3]
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s15, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
+; GFX9-NEXT: v_subb_co_u32_e64 v2, vcc, v2, v3, s[2:3]
+; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s14, v4
+; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v7, v2, s[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v7, s9
+; GFX9-NEXT: v_subb_co_u32_e64 v1, vcc, v7, v1, s[0:1]
+; GFX9-NEXT: s_ashr_i32 s0, s13, 31
+; GFX9-NEXT: s_add_u32 s8, s12, s0
+; GFX9-NEXT: s_mov_b32 s1, s0
+; GFX9-NEXT: s_addc_u32 s9, s13, s0
+; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[0:1]
+; GFX9-NEXT: v_cvt_f32_u32_e32 v9, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v10, s9
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s15, v1
+; GFX9-NEXT: v_mac_f32_e32 v9, s16, v10
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX9-NEXT: v_rcp_f32_e32 v8, v9
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[2:3]
+; GFX9-NEXT: v_mul_f32_e32 v3, s17, v8
+; GFX9-NEXT: v_mul_f32_e32 v4, s18, v3
+; GFX9-NEXT: v_trunc_f32_e32 v4, v4
+; GFX9-NEXT: v_mac_f32_e32 v3, s19, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: s_sub_u32 s2, 0, s8
+; GFX9-NEXT: s_subb_u32 s3, 0, s9
+; GFX9-NEXT: v_mul_hi_u32 v7, s2, v3
+; GFX9-NEXT: v_mul_lo_u32 v8, s2, v4
+; GFX9-NEXT: v_mul_lo_u32 v9, s3, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s2, v3
+; GFX9-NEXT: v_add_u32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u32_e32 v7, v7, v9
+; GFX9-NEXT: v_mul_lo_u32 v8, v3, v7
+; GFX9-NEXT: v_mul_hi_u32 v9, v3, v2
+; GFX9-NEXT: v_mul_hi_u32 v10, v3, v7
+; GFX9-NEXT: v_mul_hi_u32 v11, v4, v7
+; GFX9-NEXT: v_mul_lo_u32 v7, v4, v7
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
+; GFX9-NEXT: v_mul_lo_u32 v10, v4, v2
+; GFX9-NEXT: v_mul_hi_u32 v2, v4, v2
+; GFX9-NEXT: s_ashr_i32 s12, s11, 31
+; GFX9-NEXT: s_mov_b32 s13, s12
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v9, v2, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7
+; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v5, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1]
+; GFX9-NEXT: v_mul_lo_u32 v8, s2, v3
+; GFX9-NEXT: v_mul_hi_u32 v9, s2, v2
+; GFX9-NEXT: v_mul_lo_u32 v10, s3, v2
+; GFX9-NEXT: v_mul_lo_u32 v11, s2, v2
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
+; GFX9-NEXT: v_add_u32_e32 v8, v9, v8
+; GFX9-NEXT: v_add_u32_e32 v8, v8, v10
+; GFX9-NEXT: v_mul_lo_u32 v12, v2, v8
+; GFX9-NEXT: v_mul_hi_u32 v13, v2, v11
+; GFX9-NEXT: v_mul_hi_u32 v14, v2, v8
+; GFX9-NEXT: v_mul_hi_u32 v10, v3, v11
+; GFX9-NEXT: v_mul_lo_u32 v11, v3, v11
+; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v13, v12
+; GFX9-NEXT: v_mul_hi_u32 v9, v3, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v14, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v3, v8
+; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v10, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v9, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v10, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v5, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1]
+; GFX9-NEXT: s_add_u32 s0, s10, s12
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
+; GFX9-NEXT: s_addc_u32 s1, s11, s12
+; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[12:13]
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s10, v3
+; GFX9-NEXT: v_mul_hi_u32 v7, s10, v2
+; GFX9-NEXT: v_mul_hi_u32 v9, s10, v3
+; GFX9-NEXT: v_mul_hi_u32 v10, s11, v3
+; GFX9-NEXT: v_mul_lo_u32 v3, s11, v3
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
+; GFX9-NEXT: v_mul_lo_u32 v9, s11, v2
+; GFX9-NEXT: v_mul_hi_u32 v2, s11, v2
+; GFX9-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX9-NEXT: v_xor_b32_e32 v1, s6, v1
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v9, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v2, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, s8, v3
+; GFX9-NEXT: v_mul_hi_u32 v4, s8, v2
+; GFX9-NEXT: v_mul_lo_u32 v5, s9, v2
+; GFX9-NEXT: v_mul_lo_u32 v2, s8, v2
+; GFX9-NEXT: v_mov_b32_e32 v8, s6
+; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
+; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s6, v0
+; GFX9-NEXT: v_sub_co_u32_e64 v2, s[0:1], s10, v2
+; GFX9-NEXT: v_sub_u32_e32 v4, s11, v3
+; GFX9-NEXT: v_mov_b32_e32 v5, s9
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
+; GFX9-NEXT: v_subb_co_u32_e64 v4, vcc, v4, v5, s[0:1]
+; GFX9-NEXT: v_subrev_co_u32_e64 v7, s[2:3], s8, v2
+; GFX9-NEXT: v_subbrev_co_u32_e64 v8, vcc, 0, v4, s[2:3]
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc
+; GFX9-NEXT: v_subb_co_u32_e64 v4, vcc, v4, v5, s[2:3]
+; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s8, v7
+; GFX9-NEXT: v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, v9
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v8, s11
+; GFX9-NEXT: v_subb_co_u32_e64 v3, vcc, v8, v3, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v5, s[2:3]
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX9-NEXT: v_xor_b32_e32 v2, s12, v2
+; GFX9-NEXT: v_xor_b32_e32 v3, s12, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s12
+; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s12, v2
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: global_store_dwordx4 v6, v[0:3], s[4:5]
+; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = srem <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out
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