[llvm] 260f90b - [AArch64] Add some missing Neoverse features
Sjoerd Meijer via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 19 01:18:55 PST 2021
Author: Sjoerd Meijer
Date: 2021-02-19T09:18:35Z
New Revision: 260f90bb3d1aef90764de3506f86dedd1339e37c
URL: https://github.com/llvm/llvm-project/commit/260f90bb3d1aef90764de3506f86dedd1339e37c
DIFF: https://github.com/llvm/llvm-project/commit/260f90bb3d1aef90764de3506f86dedd1339e37c.diff
LOG: [AArch64] Add some missing Neoverse features
This enables AES fusion and the post RA scheduler for the Neoverse cores.
And while we are it also for the A55 that we had missed earlier.
Differential Revision: https://reviews.llvm.org/D96866
Added:
Modified:
clang/test/Driver/aarch64-cpus.c
llvm/lib/Target/AArch64/AArch64.td
llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
Removed:
################################################################################
diff --git a/clang/test/Driver/aarch64-cpus.c b/clang/test/Driver/aarch64-cpus.c
index 7ac2473915e8..5b9bd5207792 100644
--- a/clang/test/Driver/aarch64-cpus.c
+++ b/clang/test/Driver/aarch64-cpus.c
@@ -185,8 +185,14 @@
// CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
// RUN: %clang -target aarch64 -mcpu=cortex-a78c -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A78C %s
// CORTEX-A78C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78c"
+// RUN: %clang -target aarch64 -mcpu=neoverse-e1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-E1 %s
+// NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-e1"
// RUN: %clang -target aarch64 -mcpu=neoverse-v1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V1 %s
// NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v1"
+// RUN: %clang -target aarch64 -mcpu=neoverse-n1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N1 %s
+// NEOVERSE-N1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n1"
+// RUN: %clang -target aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N2 %s
+// NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n2"
// RUN: %clang -target aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEXR82 %s
// CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
@@ -788,9 +794,6 @@
// RUN: %clang -target aarch64 -march=armv8-a+ras -### -c %s 2>&1 | FileCheck -check-prefix=V8ARAS -check-prefix=GENERIC %s
// V8ARAS: "-target-feature" "+ras"
-// RUN: %clang -target aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N2 %s
-// NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n2"
-
// ================== Check whether -march accepts mixed-case values.
// RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s
// RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 762855207d2b..bdf2e517deda 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -594,7 +594,9 @@ def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
FeatureFullFP16,
FeatureDotProd,
FeatureRCPC,
- FeaturePerfMon
+ FeaturePerfMon,
+ FeaturePostRAScheduler,
+ FeatureUseAA
]>;
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
@@ -728,7 +730,7 @@ def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
"CortexR82",
"Cortex-R82 ARM Processors", [
FeaturePostRAScheduler,
- // TODO: crypto and FuseAES
+ FeatureUseAA,
// All other features are implied by v8_0r ops:
HasV8_0rOps,
]>;
@@ -977,6 +979,9 @@ def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily",
FeatureNEON,
FeatureRCPC,
FeatureSSBS,
+ FeaturePostRAScheduler,
+ FeatureUseAA,
+ FeatureFuseAES,
]>;
def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily",
@@ -991,6 +996,9 @@ def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily",
FeatureRCPC,
FeatureSPE,
FeatureSSBS,
+ FeaturePostRAScheduler,
+ FeatureUseAA,
+ FeatureFuseAES,
]>;
def ProcNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily",
@@ -1003,7 +1011,12 @@ def ProcNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily",
FeatureMTE,
FeatureSVE2,
FeatureSVE2BitPerm,
- FeatureTRBE]>;
+ FeatureTRBE,
+ FeaturePostRAScheduler,
+ FeatureUseAA,
+ FeatureCrypto,
+ FeatureFuseAES,
+ ]>;
def ProcNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily",
"NeoverseV1",
@@ -1020,6 +1033,7 @@ def ProcNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily",
FeatureNEON,
FeaturePerfMon,
FeaturePostRAScheduler,
+ FeatureUseAA,
FeatureRandGen,
FeatureSPE,
FeatureSSBS,
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-aes.ll b/llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
index ef01326f376c..2e6139a339f9 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
@@ -10,6 +10,10 @@
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a78 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a78c| FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-x1 | FileCheck %s
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-e1 | FileCheck %s
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n1 | FileCheck %s
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n2 | FileCheck %s
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v1 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 | FileCheck %s
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