[PATCH] D96959: [RISCV] Support extraction of misaligned subvectors

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:799
+RISCVVLMUL RISCVTargetLowering::getLMUL(MVT VT) {
+  switch (VT.getSizeInBits().getKnownMinValue() / 8) {
+  default:
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craig.topper wrote:
> I kind of wonder if we should remove this division and multiply all the case values by 8. Right now we don't really verify that the KnownMinValue is divisible by 8 without remainder
Probably a good idea, yes. That's why I hacked in `getRegClassIDForVecVT` in a previous patch which treats `i1` separately. This was just moved from RISCVISelDAGToDAG, so I'm thinking it'd be better to fix that up afterwards? Then it can receive testing in isolation.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2211
+      VT.getVectorElementType(),
+      64 / VT.getVectorElementType().getSizeInBits());
+}
----------------
craig.topper wrote:
> Should we start using RVVBitsPerBlock for 64's like this?
Yes, good suggestion.


Repository:
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  https://reviews.llvm.org/D96959/new/

https://reviews.llvm.org/D96959