[PATCH] D94928: [llvm-mca] Add support for in-order CPUs
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 19 00:52:46 PST 2021
dmgreen added a comment.
Thanks for working on this, it looks like it will be very useful.
================
Comment at: llvm/lib/MCA/Stages/InOrderIssueStage.cpp:81
+
+ assert(ReadAdvance >= 0);
+ assert(WS->getCyclesLeft() != UNKNOWN_CYCLES);
----------------
How come this asserts on ReadAdvance < 0? I though it was relatively common to have certain instructions requiring operands before the main stage the pipeline is based on.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D94928/new/
https://reviews.llvm.org/D94928
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