[PATCH] D96959: [RISCV] Support extraction of misaligned subvectors

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:799
+RISCVVLMUL RISCVTargetLowering::getLMUL(MVT VT) {
+  switch (VT.getSizeInBits().getKnownMinValue() / 8) {
+  default:
----------------
I kind of wonder if we should remove this division and multiply all the case values by 8. Right now we don't really verify that the KnownMinValue is divisible by 8 without remainder


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2211
+      VT.getVectorElementType(),
+      64 / VT.getVectorElementType().getSizeInBits());
+}
----------------
Should we start using RVVBitsPerBlock for 64's like this?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96959/new/

https://reviews.llvm.org/D96959