[PATCH] D96661: [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rv32Zbp.ll:2879
   %and1 = and i64 %shl, 4919131752989213764
-  %or = or i64 %and1, %and
+  %or = or i64 %and, %and1
   %shr = lshr i64 %a, 1
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frasercrmck wrote:
> Are these changes in operand order creating cases that weren't previously optimized? I take it it's not now required for the optimization to work.
Tablegen would automatically generate patterns for all permutations of the operands for the two ORs, but we weren't testing it. I changed the tests to make sure my commuting and associativity worked. Each test case should have a different permutation now.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96661/new/

https://reviews.llvm.org/D96661