[PATCH] D96910: [RISCV] Add support for fixed vector sign/zero extend from mask types.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG792627be359e: [RISCV] Add support for fixed vector sign/zero extend from mask types. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D96910?vs=324452&id=324671#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96910/new/

https://reviews.llvm.org/D96910

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D96910.324671.patch
Type: text/x-patch
Size: 10125 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210218/16c36222/attachment.bin>