[PATCH] D96921: [RISCV] Support isel of scalable vector bitcasts

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:763
+        Node->getOperand(0).getSimpleValueType().isScalableVector()) {
+      ReplaceUses(SDValue(Node, 0), Node->getOperand(0));
+      CurDAG->RemoveDeadNode(Node);
----------------
frasercrmck wrote:
> I'm kind of surprised this works - doesn't `ReplaceUses` expect the "from" and "to" to have the same type?
It doesn't check. Here is what tablegen generates for AArch64

```
/*278776*/    OPC_CompleteMatch, 1, 0,-                                                                                                                                                                                                                                                                                             
               // Src: (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv8bf16] }:$src) - Complexity = 3                                                                                                                                                                                                                                      
               // Dst: ZPR:{ *:[nxv2f64] }:$src
```

CompleteMatch calls ReplaceUses, there's an assert above the call to ReplaceUses in CompleteMatch that checks if the VT matches OR that the type has the same number of bits.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96921/new/

https://reviews.llvm.org/D96921