[llvm] a1e5388 - [Verifier] add tests for vector reductions; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2021-02-18T10:35:38-05:00
New Revision: a1e5388a7ca1d0d46ed84ac2dedf52ade7ac8200

URL: https://github.com/llvm/llvm-project/commit/a1e5388a7ca1d0d46ed84ac2dedf52ade7ac8200
DIFF: https://github.com/llvm/llvm-project/commit/a1e5388a7ca1d0d46ed84ac2dedf52ade7ac8200.diff

LOG: [Verifier] add tests for vector reductions; NFC

Checking existing functionality before D96904.

Added: 
    llvm/test/Verifier/reduction-intrinsics.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Verifier/reduction-intrinsics.ll b/llvm/test/Verifier/reduction-intrinsics.ll
new file mode 100644
index 000000000000..8eef826b6b93
--- /dev/null
+++ b/llvm/test/Verifier/reduction-intrinsics.ll
@@ -0,0 +1,40 @@
+; RUN: not opt -S -verify < %s 2>&1 | FileCheck %s
+
+; Reject a vector reduction with a non-vector argument.
+
+define float @reduce_vector_not_vec_arg(float %x) {
+; CHECK: Intrinsic has incorrect argument type!
+  %r0 = call float @llvm.vector.reduce.fmax.f32(float %x)
+  ret float %r0
+}
+
+define i32 @reduce_vector_not_vec_arg2(i32 %x) {
+; CHECK: Intrinsic has incorrect argument type!
+  %r0 = call i32 @llvm.vector.reduce.smax.i32(i32 %x)
+  ret i32 %r0
+}
+
+; Type mismatch for start value.
+
+define float @fadd_match_arg_types(<4 x float> %x) {
+; CHECK: Intrinsic has incorrect argument type!
+  %r = call float @llvm.vector.reduce.fadd.v4f32(double 0.0, <4 x float> %x)
+  ret float %r
+}
+
+; Wrong result type.
+
+define i64 @result_too_wide(<4 x i32> %x) {
+; CHECK: Intrinsic has incorrect return type!
+  %r = call i64 @llvm.vector.reduce.add.v4i32(<4 x i32> %x)
+  ret i64 %r
+}
+
+declare float @llvm.vector.reduce.umin.v4f32(<4 x float>)
+declare i32* @llvm.vector.reduce.or.v4p0i32(<4 x i32*>)
+declare i32 @llvm.vector.reduce.fadd.v4i32(i32, <4 x i32>)
+declare float @llvm.vector.reduce.fadd.v4f32(double, <4 x float>)
+declare i32* @llvm.vector.reduce.fmin.v4p0i32(<4 x i32*>)
+declare float @llvm.vector.reduce.fmax.f32(float)
+declare i32 @llvm.vector.reduce.smax.i32(i32)
+declare i64 @llvm.vector.reduce.add.v4i32(<4 x i32>)