[PATCH] D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes updated this revision to Diff 324619.
c-rhodes edited the summary of this revision.
c-rhodes added a comment.

Changes:

- As proposed by @sdesmalen, the intrinsic now supports two variants based on the sign of the immediate, where a negative immediate is a trailing element count and a positive immediate an index.
- Following the discussion on the reverse intrinsic (D94883 <https://reviews.llvm.org/D94883>) around whether named shufflevector intrinsics should support fixed vectors, I've opted for the same approach to make it explicit in the LangRef that whilst these instructions are experimental `shufflevector` should be used for fixed-width vectors. The changes to `InstCombineCalls` to map this intrinsic to shufflevector as an IR transform have been dropped.
- `ExpandVectorSpliceThroughStack` has been moved to TLI under `expandVectorSplice` which is reused by `DAGTypeLegalizer::SplitVecRes_VECTOR_SPLICE`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94708/new/

https://reviews.llvm.org/D94708

Files:
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

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