[PATCH] D96923: [NFC][RISCV] Use concise way to describe load/store instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb97d8b32c32b: [NFC][RISCV] Use concise way to describe load/store instructions. (authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96923/new/

https://reviews.llvm.org/D96923

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -71,15 +71,9 @@
                                         VReg reg_class>
 {
   defvar load_instr =
-    !cond(!eq(vlmul.value, V_M1.value): !cast<Instruction>("VL1RE"#sew#"_V"),
-          !eq(vlmul.value, V_M2.value): !cast<Instruction>("VL2RE"#sew#"_V"),
-          !eq(vlmul.value, V_M4.value): !cast<Instruction>("VL4RE"#sew#"_V"),
-          !eq(vlmul.value, V_M8.value): !cast<Instruction>("VL8RE"#sew#"_V"));
+    !cast<Instruction>("VL"#!substr(vlmul.MX, 1)#"RE"#sew#"_V");
   defvar store_instr =
-    !cond(!eq(vlmul.value, V_M1.value): VS1R_V,
-          !eq(vlmul.value, V_M2.value): VS2R_V,
-          !eq(vlmul.value, V_M4.value): VS4R_V,
-          !eq(vlmul.value, V_M8.value): VS8R_V);
+    !cast<Instruction>("VS"#!substr(vlmul.MX, 1)#"R_V");
 
   // Load
   def : Pat<(type (load BaseAddr:$rs1)),


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