[llvm] b97d8b3 - [NFC][RISCV] Use concise way to describe load/store instructions.

[Hsiangkai Wang via llvm-commits]

Author: Hsiangkai Wang
Date: 2021-02-18T22:17:00+08:00
New Revision: b97d8b32c32bd38ab5f7aa75a25dc31a9564fdc2

URL: https://github.com/llvm/llvm-project/commit/b97d8b32c32bd38ab5f7aa75a25dc31a9564fdc2
DIFF: https://github.com/llvm/llvm-project/commit/b97d8b32c32bd38ab5f7aa75a25dc31a9564fdc2.diff

LOG: [NFC][RISCV] Use concise way to describe load/store instructions.

Differential Revision: https://reviews.llvm.org/D96923

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 2c845af85c8f..a98bb0f13c49 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -71,15 +71,9 @@ multiclass VPatUSLoadStoreWholeVRSDNode<LLVMType type,
                                         VReg reg_class>
 {
   defvar load_instr =
-    !cond(!eq(vlmul.value, V_M1.value): !cast<Instruction>("VL1RE"#sew#"_V"),
-          !eq(vlmul.value, V_M2.value): !cast<Instruction>("VL2RE"#sew#"_V"),
-          !eq(vlmul.value, V_M4.value): !cast<Instruction>("VL4RE"#sew#"_V"),
-          !eq(vlmul.value, V_M8.value): !cast<Instruction>("VL8RE"#sew#"_V"));
+    !cast<Instruction>("VL"#!substr(vlmul.MX, 1)#"RE"#sew#"_V");
   defvar store_instr =
-    !cond(!eq(vlmul.value, V_M1.value): VS1R_V,
-          !eq(vlmul.value, V_M2.value): VS2R_V,
-          !eq(vlmul.value, V_M4.value): VS4R_V,
-          !eq(vlmul.value, V_M8.value): VS8R_V);
+    !cast<Instruction>("VS"#!substr(vlmul.MX, 1)#"R_V");
 
   // Load
   def : Pat<(type (load BaseAddr:$rs1)),