[llvm] ae1e6c3 - [RISCV] Rewrite assert to not give unused variable warnings in Release builds

[Benjamin Kramer via llvm-commits]

Author: Benjamin Kramer
Date: 2021-02-18T11:42:36+01:00
New Revision: ae1e6c35570116607a4895120e6c0a524bc66b1b

URL: https://github.com/llvm/llvm-project/commit/ae1e6c35570116607a4895120e6c0a524bc66b1b
DIFF: https://github.com/llvm/llvm-project/commit/ae1e6c35570116607a4895120e6c0a524bc66b1b.diff

LOG: [RISCV] Rewrite assert to not give unused variable warnings in Release builds

NFCI

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 1c3d0cfc2fbb..fba8da67bc76 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -835,10 +835,9 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       // If we haven't set a SubRegIdx, then we must be going between LMUL<=1
       // types (VR -> VR). This can be done as a copy.
       if (SubRegIdx == RISCV::NoSubRegister) {
-        unsigned RegClassID = getRegClassIDForVecVT(VT);
         unsigned InRegClassID = getRegClassIDForVecVT(InVT);
-        assert(RegClassID == InRegClassID &&
-               RegClassID == RISCV::VRRegClassID &&
+        assert(getRegClassIDForVecVT(VT) == RISCV::VRRegClassID &&
+               InRegClassID == RISCV::VRRegClassID &&
                "Unexpected subvector extraction");
         SDValue RC =
             CurDAG->getTargetConstant(InRegClassID, DL, Subtarget->getXLenVT());