[PATCH] D96910: [RISCV] Add support for fixed vector sign/zero extend from mask types.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I must have added that before I fixed the RV32 behavior. Not sure why I didn’t see the error unless I forgot to run check-llvm after running the update script.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96910/new/

https://reviews.llvm.org/D96910