[PATCH] D96937: [RISCV] Fix bugs in pseudo instructions for masked segment load.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:506
+                 !eq(VRegClass, VRN8M1) : VRN8M1NoV0,
                  !eq(1, 1) : VRegClass);
 }
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rogfer01 wrote:
> Now that we're here, is it possible to replace `!eq(1, 1)` with `true`?
I will do it. Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96937/new/

https://reviews.llvm.org/D96937