[PATCH] D96894: [RISCV] Split zvlsseg searchable table into 4 separate tables. Index by properties rather than intrinsic ID.

Hsiangkai Wang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 17 23:28:43 PST 2021


HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1103
       RISCVVPseudo,
-      RISCVZvlsseg<PseudoToIntrinsic<NAME, false>.Intrinsic, EEW, VLMul, LMUL> {
+      RISCVVLXSEG<NF, 0, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
----------------
/*Masked*/0


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1124
       RISCVVPseudo,
-      RISCVZvlsseg<PseudoToIntrinsic<NAME, true>.Intrinsic, EEW, VLMul, LMUL> {
+      RISCVVLXSEG<NF, 1, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 1;
----------------
/*Masked*/1


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1209
       RISCVVPseudo,
-      RISCVZvlsseg<PseudoToIntrinsic<NAME, false>.Intrinsic, EEW, VLMul, LMUL> {
+      RISCVVSXSEG<NF, 0, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 0;
----------------
/*Masked*/0


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1227
       RISCVVPseudo,
-      RISCVZvlsseg<PseudoToIntrinsic<NAME, true>.Intrinsic, EEW, VLMul, LMUL> {
+      RISCVVSXSEG<NF, 1, Ordered, EEW, VLMul, LMUL> {
   let mayLoad = 0;
----------------
/*Masked*/1


Repository:
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  https://reviews.llvm.org/D96894/new/

https://reviews.llvm.org/D96894



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