[PATCH] D96927: [X86] Zero AMX config buffer for non AVX512 cases.

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added inline comments.


================
Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:127
+        .addReg(Ymm);
+  } else {
+    Register Xmm = MRI->createVirtualRegister(&X86::VR128RegClass);
----------------
LuoYuanke wrote:
> SSE2 is by default enabled?
SSE2 is enabled on X64 by default, though it can be disabled. I added an assertion for it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96927/new/

https://reviews.llvm.org/D96927