[llvm] 6f30d00 - [RISCV] Merge the vsetvli and vsetvlimax intrinsic selection

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-02-17T10:08:33-08:00
New Revision: 6f30d0035a8e5ddbffdb940a88c4ab62525face1

URL: https://github.com/llvm/llvm-project/commit/6f30d0035a8e5ddbffdb940a88c4ab62525face1
DIFF: https://github.com/llvm/llvm-project/commit/6f30d0035a8e5ddbffdb940a88c4ab62525face1.diff

LOG: [RISCV] Merge the vsetvli and vsetvlimax intrinsic selection

These have very similar code just with a different number of
operands and handling for vsetivl.

Differential Revision: https://reviews.llvm.org/D96834

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index ec196ce70296..158fc7d5db06 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -608,31 +608,42 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     default:
       break;
 
-    case Intrinsic::riscv_vsetvli: {
+    case Intrinsic::riscv_vsetvli:
+    case Intrinsic::riscv_vsetvlimax: {
       if (!Subtarget->hasStdExtV())
         break;
 
-      assert(Node->getNumOperands() == 5);
+      bool VLMax = IntNo == Intrinsic::riscv_vsetvlimax;
+      unsigned Offset = VLMax ? 2 : 3;
+
+      assert(Node->getNumOperands() == Offset + 2 &&
+             "Unexpected number of operands");
 
       RISCVVSEW VSEW =
-          static_cast<RISCVVSEW>(Node->getConstantOperandVal(3) & 0x7);
-      RISCVVLMUL VLMul =
-          static_cast<RISCVVLMUL>(Node->getConstantOperandVal(4) & 0x7);
+          static_cast<RISCVVSEW>(Node->getConstantOperandVal(Offset) & 0x7);
+      RISCVVLMUL VLMul = static_cast<RISCVVLMUL>(
+          Node->getConstantOperandVal(Offset + 1) & 0x7);
 
       unsigned VTypeI = RISCVVType::encodeVTYPE(
           VLMul, VSEW, /*TailAgnostic*/ true, /*MaskAgnostic*/ false);
       SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT);
 
-      SDValue VLOperand = Node->getOperand(2);
-      if (auto *C = dyn_cast<ConstantSDNode>(VLOperand)) {
-        uint64_t AVL = C->getZExtValue();
-        if (isUInt<5>(AVL)) {
-          SDValue VLImm = CurDAG->getTargetConstant(AVL, DL, XLenVT);
-          ReplaceNode(Node,
-                      CurDAG->getMachineNode(RISCV::PseudoVSETIVLI, DL, XLenVT,
+      SDValue VLOperand;
+      if (VLMax) {
+        VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT);
+      } else {
+        VLOperand = Node->getOperand(2);
+
+        if (auto *C = dyn_cast<ConstantSDNode>(VLOperand)) {
+          uint64_t AVL = C->getZExtValue();
+          if (isUInt<5>(AVL)) {
+            SDValue VLImm = CurDAG->getTargetConstant(AVL, DL, XLenVT);
+            ReplaceNode(
+                Node, CurDAG->getMachineNode(RISCV::PseudoVSETIVLI, DL, XLenVT,
                                              MVT::Other, VLImm, VTypeIOp,
                                              /* Chain */ Node->getOperand(0)));
-          return;
+            return;
+          }
         }
       }
 
@@ -642,28 +653,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
                                          /* Chain */ Node->getOperand(0)));
       return;
     }
-    case Intrinsic::riscv_vsetvlimax: {
-      if (!Subtarget->hasStdExtV())
-        break;
-
-      assert(Node->getNumOperands() == 4);
-
-      RISCVVSEW VSEW =
-          static_cast<RISCVVSEW>(Node->getConstantOperandVal(2) & 0x7);
-      RISCVVLMUL VLMul =
-          static_cast<RISCVVLMUL>(Node->getConstantOperandVal(3) & 0x7);
-
-      unsigned VTypeI = RISCVVType::encodeVTYPE(
-          VLMul, VSEW, /*TailAgnostic*/ true, /*MaskAgnostic*/ false);
-      SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT);
-
-      SDValue VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT);
-      ReplaceNode(Node,
-                  CurDAG->getMachineNode(RISCV::PseudoVSETVLI, DL, XLenVT,
-                                         MVT::Other, VLOperand, VTypeIOp,
-                                         /* Chain */ Node->getOperand(0)));
-      return;
-    }
     case Intrinsic::riscv_vlseg2:
     case Intrinsic::riscv_vlseg3:
     case Intrinsic::riscv_vlseg4: