[llvm] f78aa8b - [LSR] Add a flag that overrides the target's preferred addressing mode
Sjoerd Meijer via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 17 08:50:59 PST 2021
Author: Sjoerd Meijer
Date: 2021-02-17T16:50:21Z
New Revision: f78aa8b2c2ebe021b09f35a25e60a8688c757638
URL: https://github.com/llvm/llvm-project/commit/f78aa8b2c2ebe021b09f35a25e60a8688c757638
DIFF: https://github.com/llvm/llvm-project/commit/f78aa8b2c2ebe021b09f35a25e60a8688c757638.diff
LOG: [LSR] Add a flag that overrides the target's preferred addressing mode
This adds a new flag -lsr-preferred-addressing-mode to override the target's
preferred addressing mode. It replaces flag -lsr-backedge-indexing, which is
equivalent to preindexed addressing that is one of the options that
-lsr-preferred-addressing-mode accepts.
Differential Revision: https://reviews.llvm.org/D96855
Added:
Modified:
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
llvm/test/CodeGen/ARM/loop-indexing.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index 963fe9a9ac49..7ae7520a0b35 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -161,9 +161,18 @@ static cl::opt<bool> FilterSameScaledReg(
cl::desc("Narrow LSR search space by filtering non-optimal formulae"
" with the same ScaledReg and Scale"));
-static cl::opt<bool> EnableBackedgeIndexing(
- "lsr-backedge-indexing", cl::Hidden, cl::init(true),
- cl::desc("Enable the generation of cross iteration indexed memops"));
+static cl::opt<TTI::AddressingModeKind> PreferredAddresingMode(
+ "lsr-preferred-addressing-mode", cl::Hidden, cl::init(TTI::AMK_None),
+ cl::desc("A flag that overrides the target's preferred addressing mode."),
+ cl::values(clEnumValN(TTI::AMK_None,
+ "none",
+ "Don't prefer any addressing mode"),
+ clEnumValN(TTI::AMK_PreIndexed,
+ "preindexed",
+ "Prefer pre-indexed addressing mode"),
+ clEnumValN(TTI::AMK_PostIndexed,
+ "postindexed",
+ "Prefer post-indexed addressing mode")));
static cl::opt<unsigned> ComplexityLimit(
"lsr-complexity-limit", cl::Hidden,
@@ -3810,9 +3819,7 @@ void LSRInstance::GenerateConstantOffsetsImpl(
// means that a single pre-indexed access can be generated to become the new
// base pointer for each iteration of the loop, resulting in no extra add/sub
// instructions for pointer updating.
- bool FavorPreIndexed = EnableBackedgeIndexing &&
- AMK == TTI::AMK_PreIndexed;
- if (FavorPreIndexed && LU.Kind == LSRUse::Address) {
+ if (AMK == TTI::AMK_PreIndexed && LU.Kind == LSRUse::Address) {
if (auto *GAR = dyn_cast<SCEVAddRecExpr>(G)) {
if (auto *StepRec =
dyn_cast<SCEVConstant>(GAR->getStepRecurrence(SE))) {
@@ -5561,7 +5568,8 @@ LSRInstance::LSRInstance(Loop *L, IVUsers &IU, ScalarEvolution &SE,
const TargetTransformInfo &TTI, AssumptionCache &AC,
TargetLibraryInfo &TLI, MemorySSAUpdater *MSSAU)
: IU(IU), SE(SE), DT(DT), LI(LI), AC(AC), TLI(TLI), TTI(TTI), L(L),
- MSSAU(MSSAU), AMK(TTI.getPreferredAddressingMode(L, &SE)) {
+ MSSAU(MSSAU), AMK(PreferredAddresingMode.getNumOccurrences() > 0 ?
+ PreferredAddresingMode : TTI.getPreferredAddressingMode(L, &SE)) {
// If LoopSimplify form is not available, stay out of trouble.
if (!L->isLoopSimplifyForm())
return;
diff --git a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
index 7b80b400af40..3925c2704e7b 100644
--- a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
+++ b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
@@ -1,8 +1,19 @@
-; RUN: llc -mtriple=thumbv7em -mattr=+fp-armv8 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DEFAULT
-; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DEFAULT
-; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp -lsr-backedge-indexing=false %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLED
-; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLED
-; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp -lsr-complexity-limit=2147483647 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-COMPLEX
+; RUN: llc -mtriple=thumbv7em -mattr=+fp-armv8 %s -o - | \
+; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DEFAULT
+
+; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp %s -o - | \
+; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DEFAULT
+
+; -lsr-backedge-indexing=false
+
+; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp -lsr-preferred-addressing-mode=postindexed %s -o - | \
+; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=DISABLED
+
+; RUN: llc -mtriple=thumbv8 %s -o - | \
+; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=DISABLED
+
+; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp -lsr-complexity-limit=2147483647 %s -o - | \
+; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-COMPLEX
; CHECK-LABEL: test_qadd_2
; CHECK: @ %loop
diff --git a/llvm/test/CodeGen/ARM/loop-indexing.ll b/llvm/test/CodeGen/ARM/loop-indexing.ll
index 00d5bdce5ba3..496599f473db 100644
--- a/llvm/test/CodeGen/ARM/loop-indexing.ll
+++ b/llvm/test/CodeGen/ARM/loop-indexing.ll
@@ -1,9 +1,23 @@
-; RUN: llc --mtriple=thumbv7em -mattr=+fp-armv8 -O3 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DEFAULT --check-prefix=CHECK-T2
-; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp -O3 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DEFAULT --check-prefix=CHECK-T2
-; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp -lsr-backedge-indexing=false %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLED
+; RUN: llc --mtriple=thumbv7em -mattr=+fp-armv8 -O3 %s -o - | \
+; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DEFAULT --check-prefix=CHECK-T2
+
+; RUN: llc --mtriple=thumbv7em -mattr=+fp-armv8 -O3 -lsr-preferred-addressing-mode=none %s -o - | \
+; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=DISABLED
+
+; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp -O3 %s -o - | \
+; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DEFAULT --check-prefix=CHECK-T2
+
+; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp -lsr-preferred-addressing-mode=postindexed %s -o - | \
+; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=DISABLED
+
+; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp -lsr-preferred-addressing-mode=preindexed %s -o - | \
+; RUN: FileCheck %s --check-prefixes=CHECK,CHECK-T2
+
; RUN: llc -mtriple=thumbv8m.base %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLED
; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLED
-; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp -O3 -lsr-complexity-limit=2147483647 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-COMPLEX --check-prefix=CHECK-T2
+
+; RUN: llc -mtriple=thumbv8m.main -mattr=+fp-armv8,+dsp -O3 -lsr-complexity-limit=2147483647 %s -o - | \
+; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-COMPLEX --check-prefix=CHECK-T2
; Tests to check that post increment addressing modes are used instead of
; updating base pointers with add instructions.
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