[PATCH] D96836: [FPEnv][AArch64] Implement lowering of llvm.set.rounding

[Serge Pavlov via Phabricator via llvm-commits]

sepavloff added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/fpenv.ll:12
+; CHECK:       sub   w10, w0, #1
+; CHECK:       and   x8, x8, x9
+; CHECK:       and   w9, w10, #0x3
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simon_tatham wrote:
> This may be outside the scope of your patch, but do you have any idea why this hasn't come out as `BIC x8, x8, #0xC00000`, but instead, has carefully materialized `~0xC00000` in a register so that it can use `AND` instead of `BIC`?
Looking at A64 instruction documentation, I see that `BIC` has only `register, register` variant.


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  https://reviews.llvm.org/D96836/new/

https://reviews.llvm.org/D96836