[PATCH] D96849: [SVE][CodeGen] Expand SVE MULH[SU] and [SU]MUL_LOHI nodes

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
frasercrmck added reviewers: kmclaughlin, paulwalker-arm, cameron.mcinally, sdesmalen, efriedma.
Herald added subscribers: steven.zhang, psnobl, hiraditya, kristof.beyls, tschuett.
frasercrmck requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This patch fixes a codegen crash introduced in fde24661718c <https://reviews.llvm.org/rGfde24661718c7812a20a10e518cd853e8e060107>, where the
DAGCombiner started generating optimized MULH[SU] or [SU]MUL_LOHI nodes
unless the target opted out. The AArch64 backend cannot currently select
any of these nodes, so ensure that they are not generated in the first
place.

This issue was raised by @huihuiz in D94501 <https://reviews.llvm.org/D94501>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96849

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll


Index: llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
+++ llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
@@ -779,3 +779,27 @@
   %lshr = lshr <vscale x 2 x i64> %a, %splat
   ret <vscale x 2 x i64> %lshr
 }
+
+define <vscale x 4 x i32> @sdiv_const(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: sdiv_const:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    mov z1.s, #3 // =0x3
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    sdiv z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    ret
+entry:
+  %div = sdiv <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
+  ret <vscale x 4 x i32> %div
+}
+
+define <vscale x 4 x i32> @udiv_const(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: udiv_const:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    mov z1.s, #3 // =0x3
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    udiv z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    ret
+entry:
+  %div = udiv <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
+  ret <vscale x 4 x i32> %div
+}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1124,6 +1124,11 @@
       setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
       setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
       setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
+
+      setOperationAction(ISD::MULHU, VT, Expand);
+      setOperationAction(ISD::MULHS, VT, Expand);
+      setOperationAction(ISD::UMUL_LOHI, VT, Expand);
+      setOperationAction(ISD::SMUL_LOHI, VT, Expand);
     }
 
     // Illegal unpacked integer vector types.


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