[PATCH] D96517: [AMDGPU] Optimize SGPR to scratch spilling

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1186
+      if (!SB.TmpVGPRLive) {
+        // Only spill inactive lanes
+        if (!SB.SavedExecLoOnly || AMDGPU::isGFX10Plus(ST)) {
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I don't think limiting the lanes helps any. Are you 100% sure this is worth the extra complexity? Does it actually reduce bandwidth?


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1187
+        // Only spill inactive lanes
+        if (!SB.SavedExecLoOnly || AMDGPU::isGFX10Plus(ST)) {
+          // _saveexec_b32 instructions are only available on gfx10+
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Specific feature checks are better than generation version checks


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Comment at: llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll:764
 ; GCN-NEXT:    ;;#ASMEND
 ; GCN-NEXT:    ;;#FAKE_DEF v0
 ; GCN-NEXT:    s_not_b64 exec, exec
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I thought you renamed this?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96517/new/

https://reviews.llvm.org/D96517