[PATCH] D96741: [RISCV] Add support for fixed vector mask logic operations.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG07ca13fe0766: [RISCV] Add support for fixed vector mask logic operations. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D96741?vs=323862&id=324038#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96741/new/

https://reviews.llvm.org/D96741

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll

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