[PATCH] D96596: [AArch64] Convert CMP/SELECT sign patterns to OR & ASR.

[Florian Hahn via Phabricator via llvm-commits]

fhahn marked an inline comment as done.
fhahn added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15007
+        SplatLHS->getConstantSplatNode()->isOne() &&
+        SplatRHS->getConstantSplatNode() &&
+        SplatRHS->getConstantSplatNode()->isAllOnesValue() && CmpRHS &&
----------------
dmgreen wrote:
> These is a ISD::isConstantSplatVectorAllOnes, but I don't know if there is one for "IsOne"
I updated the code to use `isConstantSplatVectorAllOnes` and `isConstantSplatVector` for the OneValue cause.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D96596/new/

https://reviews.llvm.org/D96596