[PATCH] D96028: [RISCV] Add patterns for scalable-vector fabs & fcopysign

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck marked an inline comment as done.
frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2759
+      break;
+    // There is a form of VFSGNJ which injects the negated sign of its second
+    // operand. Try and bubble any FNEG up after the extend/round to produce
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craig.topper wrote:
> Should we avoid doing this if the extend/round is used elsewhere so we don't end up with extends/rounds of both the original and negated value?
Yeah probably because extends/rounds are typically more expensive than fneg. Will update.


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https://reviews.llvm.org/D96028