[PATCH] D96681: [RISCV][LegalizeTypes] Try to expand BITREVERSE before promoting if the promoted BITREVERSE would expand anyway.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:7129
+  // and finally the i1 pairs.
+  // TODO: We can easily support i4/i2 legal types if any target ever does.
+  if (Sz >= 8 && isPowerOf2_32(Sz)) {
----------------
RKSimon wrote:
> Isn't this dealt with at the bottom of the function?
I think the code at the bottom would generate one additional instruction for i4 and the same number of instructions for i2.


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  https://reviews.llvm.org/D96681/new/

https://reviews.llvm.org/D96681