[PATCH] D96639: [AMDGPU] Add two TSFlags: IsAtomicNoRtn and IsAtomicRtn

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp:572
         setExpScore(&Inst, TII, TRI, MRI, 0, CurrScore);
-      } else if (AMDGPU::getAtomicNoRetOp(Inst.getOpcode()) != -1) {
         setExpScore(
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@foad do I get it right, all MIMG atomics are rtn only? MIMG has never used AtomicNoRet map, so this branch was dead. Maybe we were missing to wait for exp, maybe they all mayStore, or maybe it is really dead an unused. Potentially you will see some extra exp waits, but it didn't appear in our tests. That said I am afraid test coverage for waitcounts is not sufficient.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96639/new/

https://reviews.llvm.org/D96639