[PATCH] D96469: [AMDGPU] WIP: use single cache policy operand

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 323186.
rampitec marked an inline comment as done.
rampitec added a comment.
Herald added a subscriber: jfb.

Added full FLAT support. Atomics with forced GLC work.

Ideally I want to have no special cpol_glc1 and cpol_glc0 operands, so that it would be alsways possible to just query named operand cpol, but that would need 2 bits in TSFlags. Otherwise it does not seem possible to make sure if we have forced 1 or 0 glc bit. At least this patch is no worse than using glc1 operand as now.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96469/new/

https://reviews.llvm.org/D96469

Files:
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  llvm/lib/Target/AMDGPU/FLATInstructions.td
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
  llvm/lib/Target/AMDGPU/SIDefines.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/test/MC/AMDGPU/cpol-err.s
  llvm/test/MC/AMDGPU/flat-gfx10.s
  llvm/test/MC/AMDGPU/flat-gfx9.s

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