[PATCH] D96424: [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks. It looks like this could do with more half tests.



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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2133
+  // Zd = Za + Zn * Zm
+  def : Pat<(nxv8f16 (AArch64fma_p nxv8i1:$P, nxv8f16:$Zn, nxv8f16:$Zm, nxv8f16:$Za)),
+            (FMLA_ZPZZZ_UNDEF_H $P, ZPR:$Za, ZPR:$Zn, ZPR:$Zm)>;
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Should there be nxv4f16 and nxv2f16 patterns?

It may also make sense to make multipatterns from these. They all just differ in a similar way to how TriOpFrag is used.

And it would probably be best to keep these close to the instructions they create, unless there is a reason have them separate.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D96424/new/

https://reviews.llvm.org/D96424