[llvm] d5adba1 - [CodeGen] Use range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 13 20:42:11 PST 2021
Author: Kazu Hirata
Date: 2021-02-13T20:41:39-08:00
New Revision: d5adba10f0499b8c59b91228e8b58e1122a76428
URL: https://github.com/llvm/llvm-project/commit/d5adba10f0499b8c59b91228e8b58e1122a76428
DIFF: https://github.com/llvm/llvm-project/commit/d5adba10f0499b8c59b91228e8b58e1122a76428.diff
LOG: [CodeGen] Use range-based for loops (NFC)
Added:
Modified:
llvm/lib/CodeGen/EarlyIfConversion.cpp
llvm/lib/CodeGen/LatencyPriorityQueue.cpp
llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
llvm/lib/CodeGen/LiveDebugVariables.cpp
llvm/lib/CodeGen/LiveInterval.cpp
llvm/lib/CodeGen/LivePhysRegs.cpp
llvm/lib/CodeGen/LiveVariables.cpp
llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index cf7d93d6a33a..f8095e95ddcb 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -410,9 +410,8 @@ bool SSAIfConv::findInsertionPoint() {
if (!LiveRegUnits.empty()) {
LLVM_DEBUG({
dbgs() << "Would clobber";
- for (SparseSet<unsigned>::const_iterator
- i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i)
- dbgs() << ' ' << printRegUnit(*i, TRI);
+ for (unsigned LRU : LiveRegUnits)
+ dbgs() << ' ' << printRegUnit(LRU, TRI);
dbgs() << " live before " << *I;
});
continue;
diff --git a/llvm/lib/CodeGen/LatencyPriorityQueue.cpp b/llvm/lib/CodeGen/LatencyPriorityQueue.cpp
index 8a7a41d0f763..c3e0553418a5 100644
--- a/llvm/lib/CodeGen/LatencyPriorityQueue.cpp
+++ b/llvm/lib/CodeGen/LatencyPriorityQueue.cpp
@@ -55,9 +55,8 @@ bool latency_sort::operator()(const SUnit *LHS, const SUnit *RHS) const {
/// of SU, return it, otherwise return null.
SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) {
SUnit *OnlyAvailablePred = nullptr;
- for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
- I != E; ++I) {
- SUnit &Pred = *I->getSUnit();
+ for (const SDep &P : SU->Preds) {
+ SUnit &Pred = *P.getSUnit();
if (!Pred.isScheduled) {
// We found an available, but not scheduled, predecessor. If it's the
// only one we have found, keep track of it... otherwise give up.
@@ -90,10 +89,8 @@ void LatencyPriorityQueue::push(SUnit *SU) {
// single predecessor has a higher priority, since scheduling it will make
// the node available.
void LatencyPriorityQueue::scheduledNode(SUnit *SU) {
- for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
- I != E; ++I) {
- AdjustPriorityOfUnscheduledPreds(I->getSUnit());
- }
+ for (const SDep &Succ : SU->Succs)
+ AdjustPriorityOfUnscheduledPreds(Succ.getSUnit());
}
/// AdjustPriorityOfUnscheduledPreds - One of the predecessors of SU was just
diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
index 70f86504dc21..5385793b258f 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
@@ -3199,10 +3199,10 @@ void InstrRefBasedLDV::initialSetup(MachineFunction &MF) {
// Compute mappings of block <=> RPO order.
ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
unsigned int RPONumber = 0;
- for (auto RI = RPOT.begin(), RE = RPOT.end(); RI != RE; ++RI) {
- OrderToBB[RPONumber] = *RI;
- BBToOrder[*RI] = RPONumber;
- BBNumToRPO[(*RI)->getNumber()] = RPONumber;
+ for (MachineBasicBlock *MBB : RPOT) {
+ OrderToBB[RPONumber] = MBB;
+ BBToOrder[MBB] = RPONumber;
+ BBNumToRPO[MBB->getNumber()] = RPONumber;
++RPONumber;
}
}
diff --git a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
index c67be3cc9c02..ad6bf25e5b8d 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
@@ -1895,9 +1895,9 @@ bool VarLocBasedLDV::ExtendRanges(MachineFunction &MF, TargetPassConfig *TPC) {
ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
unsigned int RPONumber = 0;
- for (auto RI = RPOT.begin(), RE = RPOT.end(); RI != RE; ++RI) {
- OrderToBB[RPONumber] = *RI;
- BBToOrder[*RI] = RPONumber;
+ for (MachineBasicBlock *MBB : RPOT) {
+ OrderToBB[RPONumber] = MBB;
+ BBToOrder[MBB] = RPONumber;
Worklist.push(RPONumber);
++RPONumber;
}
diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp
index 553ceb7a3df3..0d4e3385b47c 100644
--- a/llvm/lib/CodeGen/LiveDebugVariables.cpp
+++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp
@@ -732,10 +732,8 @@ bool LDVImpl::handleDebugLabel(MachineInstr &MI, SlotIndex Idx) {
bool LDVImpl::collectDebugValues(MachineFunction &mf) {
bool Changed = false;
- for (MachineFunction::iterator MFI = mf.begin(), MFE = mf.end(); MFI != MFE;
- ++MFI) {
- MachineBasicBlock *MBB = &*MFI;
- for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
+ for (MachineBasicBlock &MBB : mf) {
+ for (MachineBasicBlock::iterator MBBI = MBB.begin(), MBBE = MBB.end();
MBBI != MBBE;) {
// Use the first debug instruction in the sequence to get a SlotIndex
// for following consecutive debug instructions.
@@ -746,8 +744,8 @@ bool LDVImpl::collectDebugValues(MachineFunction &mf) {
// Debug instructions has no slot index. Use the previous
// non-debug instruction's SlotIndex as its SlotIndex.
SlotIndex Idx =
- MBBI == MBB->begin()
- ? LIS->getMBBStartIdx(MBB)
+ MBBI == MBB.begin()
+ ? LIS->getMBBStartIdx(&MBB)
: LIS->getInstructionIndex(*std::prev(MBBI)).getRegSlot();
// Handle consecutive debug instructions with the same slot index.
do {
@@ -756,7 +754,7 @@ bool LDVImpl::collectDebugValues(MachineFunction &mf) {
if ((MBBI->isDebugValue() && handleDebugValue(*MBBI, Idx)) ||
(MBBI->isDebugRef() && handleDebugInstrRef(*MBBI, Idx)) ||
(MBBI->isDebugLabel() && handleDebugLabel(*MBBI, Idx))) {
- MBBI = MBB->erase(MBBI);
+ MBBI = MBB.erase(MBBI);
Changed = true;
} else
++MBBI;
diff --git a/llvm/lib/CodeGen/LiveInterval.cpp b/llvm/lib/CodeGen/LiveInterval.cpp
index 4114fbdfab94..e1fa78d13f0c 100644
--- a/llvm/lib/CodeGen/LiveInterval.cpp
+++ b/llvm/lib/CodeGen/LiveInterval.cpp
@@ -1336,9 +1336,8 @@ unsigned ConnectedVNInfoEqClasses::Classify(const LiveRange &LR) {
const MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
assert(MBB && "Phi-def has no defining MBB");
// Connect to values live out of predecessors.
- for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
- PE = MBB->pred_end(); PI != PE; ++PI)
- if (const VNInfo *PVNI = LR.getVNInfoBefore(LIS.getMBBEndIdx(*PI)))
+ for (MachineBasicBlock *Pred : MBB->predecessors())
+ if (const VNInfo *PVNI = LR.getVNInfoBefore(LIS.getMBBEndIdx(Pred)))
EqClass.join(VNI->id, PVNI->id);
} else {
// Normal value defined by an instruction. Check for two-addr redef.
diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp
index 547970e7ab5d..fabaef9ee4d1 100644
--- a/llvm/lib/CodeGen/LivePhysRegs.cpp
+++ b/llvm/lib/CodeGen/LivePhysRegs.cpp
@@ -125,8 +125,8 @@ void LivePhysRegs::print(raw_ostream &OS) const {
return;
}
- for (const_iterator I = begin(), E = end(); I != E; ++I)
- OS << " " << printReg(*I, TRI);
+ for (MCPhysReg R : *this)
+ OS << " " << printReg(R, TRI);
OS << "\n";
}
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 49b880c30936..8201baf220fb 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -67,9 +67,8 @@ LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void LiveVariables::VarInfo::dump() const {
dbgs() << " Alive in blocks: ";
- for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
- E = AliveBlocks.end(); I != E; ++I)
- dbgs() << *I << ", ";
+ for (unsigned AB : AliveBlocks)
+ dbgs() << AB << ", ";
dbgs() << "\n Killed by:";
if (Kills.empty())
dbgs() << " No instructions.\n";
@@ -173,9 +172,8 @@ void LiveVariables::HandleVirtRegUse(Register Reg, MachineBasicBlock *MBB,
VRInfo.Kills.push_back(&MI);
// Update all dominating blocks to mark them as "known live".
- for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
- E = MBB->pred_end(); PI != E; ++PI)
- MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), *PI);
+ for (MachineBasicBlock *Pred : MBB->predecessors())
+ MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), Pred);
}
void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) {
@@ -588,19 +586,16 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
if (!PHIVarInfo[MBB->getNumber()].empty()) {
SmallVectorImpl<unsigned> &VarInfoVec = PHIVarInfo[MBB->getNumber()];
- for (SmallVectorImpl<unsigned>::iterator I = VarInfoVec.begin(),
- E = VarInfoVec.end(); I != E; ++I)
+ for (unsigned I : VarInfoVec)
// Mark it alive only in the block we are representing.
- MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
+ MarkVirtRegAliveInBlock(getVarInfo(I), MRI->getVRegDef(I)->getParent(),
MBB);
}
// MachineCSE may CSE instructions which write to non-allocatable physical
// registers across MBBs. Remember if any reserved register is liveout.
SmallSet<unsigned, 4> LiveOuts;
- for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
- SE = MBB->succ_end(); SI != SE; ++SI) {
- MachineBasicBlock *SuccMBB = *SI;
+ for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
if (SuccMBB->isEHPad())
continue;
for (const auto &LI : SuccMBB->liveins()) {
@@ -665,8 +660,8 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
// function. If so, it is due to a bug in the instruction selector or some
// other part of the code generator if this happens.
#ifndef NDEBUG
- for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
- assert(Visited.contains(&*i) && "unreachable basic block found");
+ for (const MachineBasicBlock &MBB : *MF)
+ assert(Visited.contains(&MBB) && "unreachable basic block found");
#endif
PhysRegDef.clear();
@@ -817,8 +812,8 @@ void LiveVariables::addNewBlock(MachineBasicBlock *BB,
const unsigned NumNew = BB->getNumber();
SparseBitVector<> &BV = LiveInSets[SuccBB->getNumber()];
- for (auto R = BV.begin(), E = BV.end(); R != E; R++) {
- Register VirtReg = Register::index2VirtReg(*R);
+ for (unsigned R : BV) {
+ Register VirtReg = Register::index2VirtReg(R);
LiveVariables::VarInfo &VI = getVarInfo(VirtReg);
VI.AliveBlocks.set(NumNew);
}
diff --git a/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp b/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
index ec6e693e8a46..2e99c8595cbd 100644
--- a/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
+++ b/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
@@ -176,9 +176,7 @@ void LocalStackSlotPass::AssignProtectedObjSet(
const StackObjSet &UnassignedObjs, SmallSet<int, 16> &ProtectedObjs,
MachineFrameInfo &MFI, bool StackGrowsDown, int64_t &Offset,
Align &MaxAlign) {
- for (StackObjSet::const_iterator I = UnassignedObjs.begin(),
- E = UnassignedObjs.end(); I != E; ++I) {
- int i = *I;
+ for (int i : UnassignedObjs) {
AdjustStackOffset(MFI, i, Offset, StackGrowsDown, MaxAlign);
ProtectedObjs.insert(i);
}
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