[PATCH] D96590: [AVR] Fix a bug in 16-bit shifts

[Ben Shi via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGefb1cb752bf1: [AVR] Fix a bug in 16-bit shifts (authored by benshi001).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96590/new/

https://reviews.llvm.org/D96590

Files:
  llvm/lib/Target/AVR/AVRInstrInfo.td
  llvm/test/CodeGen/AVR/shift.ll


Index: llvm/test/CodeGen/AVR/shift.ll
===================================================================
--- llvm/test/CodeGen/AVR/shift.ll
+++ llvm/test/CodeGen/AVR/shift.ll
@@ -194,6 +194,25 @@
   ret i16 %result
 }
 
+define i16 @lsl_i16_6(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f) {
+; CHECK-LABEL: lsl_i16_6
+; CHECK:       mov r24, r14
+; CHECK-NEXT:  mov r25, r15
+; CHECK-NEXT:  swap r25
+; CHECK-NEXT:  swap r24
+; CHECK-NEXT:  andi r25, 240
+; CHECK-NEXT:  eor r25, r24
+; CHECK-NEXT:  andi r24, 240
+; CHECK-NEXT:  eor r25, r24
+; CHECK-NEXT:  lsl r24
+; CHECK-NEXT:  rol r25
+; CHECK-NEXT:  lsl r24
+; CHECK-NEXT:  rol r25
+; CHECK-NEXT:  ret
+  %result = shl i16 %f, 6
+  ret i16 %result
+}
+
 define i16 @lsl_i16_9(i16 %a) {
 ; CHECK-LABEL: lsl_i16_9
 ; CHECK:       mov r25, r24
@@ -233,6 +252,25 @@
   ret i16 %result
 }
 
+define i16 @lsr_i16_6(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f) {
+; CHECK-LABEL: lsr_i16_6
+; CHECK:       mov r24, r14
+; CHECK-NEXT:  mov r25, r15
+; CHECK-NEXT:  swap r25
+; CHECK-NEXT:  swap r24
+; CHECK-NEXT:  andi r24, 15
+; CHECK-NEXT:  eor r24, r25
+; CHECK-NEXT:  andi r25, 15
+; CHECK-NEXT:  eor r24, r25
+; CHECK-NEXT:  lsr r25
+; CHECK-NEXT:  ror r24
+; CHECK-NEXT:  lsr r25
+; CHECK-NEXT:  ror r24
+; CHECK-NEXT: ret
+  %result = lshr i16 %f, 6
+  ret i16 %result
+}
+
 define i16 @lsr_i16_9(i16 %a) {
 ; CHECK-LABEL: lsr_i16_9
 ; CHECK:       mov r24, r25
Index: llvm/lib/Target/AVR/AVRInstrInfo.td
===================================================================
--- llvm/lib/Target/AVR/AVRInstrInfo.td
+++ llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1681,7 +1681,7 @@
                        "lslb7\t$rd",
                        [(set i8:$rd, (AVRlsl7 i8:$src)), (implicit SREG)]>;
 
-  def LSLW4Rd : Pseudo<(outs DREGS:$rd),
+  def LSLW4Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lslw4\t$rd",
                        [(set i16:$rd, (AVRlsl4 i16:$src)), (implicit SREG)]>;
@@ -1691,7 +1691,7 @@
                        "lslw8\t$rd",
                        [(set i16:$rd, (AVRlsl8 i16:$src)), (implicit SREG)]>;
 
-  def LSLW12Rd : Pseudo<(outs DREGS:$rd),
+  def LSLW12Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lslw12\t$rd",
                        [(set i16:$rd, (AVRlsl12 i16:$src)), (implicit SREG)]>;
@@ -1713,7 +1713,7 @@
                       "lsrw\t$rd",
                       [(set i16:$rd, (AVRlsr i16:$src)), (implicit SREG)]>;
 
-  def LSRW4Rd : Pseudo<(outs DREGS:$rd),
+  def LSRW4Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lsrw4\t$rd",
                        [(set i16:$rd, (AVRlsr4 i16:$src)), (implicit SREG)]>;
@@ -1723,7 +1723,7 @@
                        "lsrw8\t$rd",
                        [(set i16:$rd, (AVRlsr8 i16:$src)), (implicit SREG)]>;
 
-  def LSRW12Rd : Pseudo<(outs DREGS:$rd),
+  def LSRW12Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lsrw12\t$rd",
                        [(set i16:$rd, (AVRlsr12 i16:$src)), (implicit SREG)]>;


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