[llvm] efb1cb7 - [AVR] Fix a bug in 16-bit shifts

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2021-02-14T11:54:55+08:00
New Revision: efb1cb752bf12149af9c773f702a757ba9721649

URL: https://github.com/llvm/llvm-project/commit/efb1cb752bf12149af9c773f702a757ba9721649
DIFF: https://github.com/llvm/llvm-project/commit/efb1cb752bf12149af9c773f702a757ba9721649.diff

LOG: [AVR] Fix a bug in 16-bit shifts

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D96590

Added: 
    

Modified: 
    llvm/lib/Target/AVR/AVRInstrInfo.td
    llvm/test/CodeGen/AVR/shift.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td
index e967e107a1c8..3eb983688471 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1681,7 +1681,7 @@ Defs = [SREG] in
                        "lslb7\t$rd",
                        [(set i8:$rd, (AVRlsl7 i8:$src)), (implicit SREG)]>;
 
-  def LSLW4Rd : Pseudo<(outs DREGS:$rd),
+  def LSLW4Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lslw4\t$rd",
                        [(set i16:$rd, (AVRlsl4 i16:$src)), (implicit SREG)]>;
@@ -1691,7 +1691,7 @@ Defs = [SREG] in
                        "lslw8\t$rd",
                        [(set i16:$rd, (AVRlsl8 i16:$src)), (implicit SREG)]>;
 
-  def LSLW12Rd : Pseudo<(outs DREGS:$rd),
+  def LSLW12Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lslw12\t$rd",
                        [(set i16:$rd, (AVRlsl12 i16:$src)), (implicit SREG)]>;
@@ -1713,7 +1713,7 @@ Defs = [SREG] in
                       "lsrw\t$rd",
                       [(set i16:$rd, (AVRlsr i16:$src)), (implicit SREG)]>;
 
-  def LSRW4Rd : Pseudo<(outs DREGS:$rd),
+  def LSRW4Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lsrw4\t$rd",
                        [(set i16:$rd, (AVRlsr4 i16:$src)), (implicit SREG)]>;
@@ -1723,7 +1723,7 @@ Defs = [SREG] in
                        "lsrw8\t$rd",
                        [(set i16:$rd, (AVRlsr8 i16:$src)), (implicit SREG)]>;
 
-  def LSRW12Rd : Pseudo<(outs DREGS:$rd),
+  def LSRW12Rd : Pseudo<(outs DLDREGS:$rd),
                        (ins DREGS:$src),
                        "lsrw12\t$rd",
                        [(set i16:$rd, (AVRlsr12 i16:$src)), (implicit SREG)]>;

diff  --git a/llvm/test/CodeGen/AVR/shift.ll b/llvm/test/CodeGen/AVR/shift.ll
index 34042b3a1199..24bc369cf614 100644
--- a/llvm/test/CodeGen/AVR/shift.ll
+++ b/llvm/test/CodeGen/AVR/shift.ll
@@ -194,6 +194,25 @@ define i16 @lsl_i16_5(i16 %a) {
   ret i16 %result
 }
 
+define i16 @lsl_i16_6(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f) {
+; CHECK-LABEL: lsl_i16_6
+; CHECK:       mov r24, r14
+; CHECK-NEXT:  mov r25, r15
+; CHECK-NEXT:  swap r25
+; CHECK-NEXT:  swap r24
+; CHECK-NEXT:  andi r25, 240
+; CHECK-NEXT:  eor r25, r24
+; CHECK-NEXT:  andi r24, 240
+; CHECK-NEXT:  eor r25, r24
+; CHECK-NEXT:  lsl r24
+; CHECK-NEXT:  rol r25
+; CHECK-NEXT:  lsl r24
+; CHECK-NEXT:  rol r25
+; CHECK-NEXT:  ret
+  %result = shl i16 %f, 6
+  ret i16 %result
+}
+
 define i16 @lsl_i16_9(i16 %a) {
 ; CHECK-LABEL: lsl_i16_9
 ; CHECK:       mov r25, r24
@@ -233,6 +252,25 @@ define i16 @lsr_i16_5(i16 %a) {
   ret i16 %result
 }
 
+define i16 @lsr_i16_6(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f) {
+; CHECK-LABEL: lsr_i16_6
+; CHECK:       mov r24, r14
+; CHECK-NEXT:  mov r25, r15
+; CHECK-NEXT:  swap r25
+; CHECK-NEXT:  swap r24
+; CHECK-NEXT:  andi r24, 15
+; CHECK-NEXT:  eor r24, r25
+; CHECK-NEXT:  andi r25, 15
+; CHECK-NEXT:  eor r24, r25
+; CHECK-NEXT:  lsr r25
+; CHECK-NEXT:  ror r24
+; CHECK-NEXT:  lsr r25
+; CHECK-NEXT:  ror r24
+; CHECK-NEXT: ret
+  %result = lshr i16 %f, 6
+  ret i16 %result
+}
+
 define i16 @lsr_i16_9(i16 %a) {
 ; CHECK-LABEL: lsr_i16_9
 ; CHECK:       mov r24, r25