[llvm] 3520371 - [RISCV] Rename the RVVBaseAddr ComplexPattern to just BaseAddr and use it to merge some scalar load/store patterns too.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 13 12:02:47 PST 2021
Author: Craig Topper
Date: 2021-02-13T12:01:51-08:00
New Revision: 3520371ddbf99ec695dd8b32c947c2c24344ac68
URL: https://github.com/llvm/llvm-project/commit/3520371ddbf99ec695dd8b32c947c2c24344ac68
DIFF: https://github.com/llvm/llvm-project/commit/3520371ddbf99ec695dd8b32c947c2c24344ac68.diff
LOG: [RISCV] Rename the RVVBaseAddr ComplexPattern to just BaseAddr and use it to merge some scalar load/store patterns too.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoA.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 57f037f450b5..47d9a95d11b3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -915,7 +915,7 @@ bool RISCVDAGToDAGISel::SelectAddrFI(SDValue Addr, SDValue &Base) {
return false;
}
-bool RISCVDAGToDAGISel::SelectRVVBaseAddr(SDValue Addr, SDValue &Base) {
+bool RISCVDAGToDAGISel::SelectBaseAddr(SDValue Addr, SDValue &Base) {
// If this is FrameIndex, select it directly. Otherwise just let it get
// selected to a register independently.
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr))
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index 0bf5ada00f3f..a790d6051c31 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -44,7 +44,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
std::vector<SDValue> &OutOps) override;
bool SelectAddrFI(SDValue Addr, SDValue &Base);
- bool SelectRVVBaseAddr(SDValue Addr, SDValue &Base);
+ bool SelectBaseAddr(SDValue Addr, SDValue &Base);
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 707cd0478681..41661d3c3673 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -298,6 +298,7 @@ def uimm6gt32 : ImmLeaf<XLenVT, [{
// Addressing modes.
// Necessary because a frameindex can't be matched directly in a pattern.
def AddrFI : ComplexPattern<iPTR, 1, "SelectAddrFI", [frameindex], []>;
+def BaseAddr : ComplexPattern<iPTR, 1, "SelectBaseAddr">;
// Extract least significant 12 bits from an immediate value and sign extend
// them.
@@ -1110,12 +1111,9 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs
/// Loads
multiclass LdPat<PatFrag LoadOp, RVInst Inst> {
- def : Pat<(LoadOp GPR:$rs1), (Inst GPR:$rs1, 0)>;
- def : Pat<(LoadOp AddrFI:$rs1), (Inst AddrFI:$rs1, 0)>;
- def : Pat<(LoadOp (add GPR:$rs1, simm12:$imm12)),
- (Inst GPR:$rs1, simm12:$imm12)>;
- def : Pat<(LoadOp (add AddrFI:$rs1, simm12:$imm12)),
- (Inst AddrFI:$rs1, simm12:$imm12)>;
+ def : Pat<(LoadOp BaseAddr:$rs1), (Inst BaseAddr:$rs1, 0)>;
+ def : Pat<(LoadOp (add BaseAddr:$rs1, simm12:$imm12)),
+ (Inst BaseAddr:$rs1, simm12:$imm12)>;
def : Pat<(LoadOp (IsOrAdd AddrFI:$rs1, simm12:$imm12)),
(Inst AddrFI:$rs1, simm12:$imm12)>;
}
@@ -1131,12 +1129,9 @@ defm : LdPat<zextloadi16, LHU>;
/// Stores
multiclass StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
- def : Pat<(StoreOp StTy:$rs2, GPR:$rs1), (Inst StTy:$rs2, GPR:$rs1, 0)>;
- def : Pat<(StoreOp StTy:$rs2, AddrFI:$rs1), (Inst StTy:$rs2, AddrFI:$rs1, 0)>;
- def : Pat<(StoreOp StTy:$rs2, (add GPR:$rs1, simm12:$imm12)),
- (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
- def : Pat<(StoreOp StTy:$rs2, (add AddrFI:$rs1, simm12:$imm12)),
- (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
+ def : Pat<(StoreOp StTy:$rs2, BaseAddr:$rs1), (Inst StTy:$rs2, BaseAddr:$rs1, 0)>;
+ def : Pat<(StoreOp StTy:$rs2, (add BaseAddr:$rs1, simm12:$imm12)),
+ (Inst StTy:$rs2, BaseAddr:$rs1, simm12:$imm12)>;
def : Pat<(StoreOp StTy:$rs2, (IsOrAdd AddrFI:$rs1, simm12:$imm12)),
(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index 7fce37519b93..24bc59f32726 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -62,12 +62,9 @@ multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
}
multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
- def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>;
- def : Pat<(StoreOp AddrFI:$rs1, StTy:$rs2), (Inst StTy:$rs2, AddrFI:$rs1, 0)>;
- def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2),
- (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
- def : Pat<(StoreOp (add AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
- (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
+ def : Pat<(StoreOp BaseAddr:$rs1, StTy:$rs2), (Inst StTy:$rs2, BaseAddr:$rs1, 0)>;
+ def : Pat<(StoreOp (add BaseAddr:$rs1, simm12:$imm12), StTy:$rs2),
+ (Inst StTy:$rs2, BaseAddr:$rs1, simm12:$imm12)>;
def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 2976cb591993..942b4e2e223a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -37,8 +37,6 @@ def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [splat_vector,
def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [splat_vector, rv32_splat_i64], [], 2>;
def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [splat_vector, rv32_splat_i64], [], 2>;
-def RVVBaseAddr : ComplexPattern<iPTR, 1, "SelectRVVBaseAddr">;
-
class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
}
@@ -60,11 +58,11 @@ multiclass VPatUSLoadStoreSDNode<ValueType type,
defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX);
// Load
- def : Pat<(type (load RVVBaseAddr:$rs1)),
- (load_instr RVVBaseAddr:$rs1, avl, sew)>;
+ def : Pat<(type (load BaseAddr:$rs1)),
+ (load_instr BaseAddr:$rs1, avl, sew)>;
// Store
- def : Pat<(store type:$rs2, RVVBaseAddr:$rs1),
- (store_instr reg_class:$rs2, RVVBaseAddr:$rs1, avl, sew)>;
+ def : Pat<(store type:$rs2, BaseAddr:$rs1),
+ (store_instr reg_class:$rs2, BaseAddr:$rs1, avl, sew)>;
}
multiclass VPatUSLoadStoreWholeVRSDNode<LLVMType type,
@@ -84,11 +82,11 @@ multiclass VPatUSLoadStoreWholeVRSDNode<LLVMType type,
!eq(vlmul.value, V_M8.value): VS8R_V);
// Load
- def : Pat<(type (load RVVBaseAddr:$rs1)),
- (load_instr RVVBaseAddr:$rs1)>;
+ def : Pat<(type (load BaseAddr:$rs1)),
+ (load_instr BaseAddr:$rs1)>;
// Store
- def : Pat<(store type:$rs2, RVVBaseAddr:$rs1),
- (store_instr reg_class:$rs2, RVVBaseAddr:$rs1)>;
+ def : Pat<(store type:$rs2, BaseAddr:$rs1),
+ (store_instr reg_class:$rs2, BaseAddr:$rs1)>;
}
multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m>
@@ -96,11 +94,11 @@ multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m>
defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#m.BX);
defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#m.BX);
// Load
- def : Pat<(m.Mask (load RVVBaseAddr:$rs1)),
- (load_instr RVVBaseAddr:$rs1, m.AVL, m.SEW)>;
+ def : Pat<(m.Mask (load BaseAddr:$rs1)),
+ (load_instr BaseAddr:$rs1, m.AVL, m.SEW)>;
// Store
- def : Pat<(store m.Mask:$rs2, RVVBaseAddr:$rs1),
- (store_instr VR:$rs2, RVVBaseAddr:$rs1, m.AVL, m.SEW)>;
+ def : Pat<(store m.Mask:$rs2, BaseAddr:$rs1),
+ (store_instr VR:$rs2, BaseAddr:$rs1, m.AVL, m.SEW)>;
}
class VPatBinarySDNode_VV<SDNode vop,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 1ddd8af76148..321a80a92389 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -313,22 +313,22 @@ foreach vti = AllVectors in {
defvar load_instr = !cast<Instruction>("PseudoVLE"#vti.SEW#"_V_"#vti.LMul.MX);
defvar store_instr = !cast<Instruction>("PseudoVSE"#vti.SEW#"_V_"#vti.LMul.MX);
// Load
- def : Pat<(vti.Vector (riscv_vle_vl RVVBaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))),
- (load_instr RVVBaseAddr:$rs1, GPR:$vl, vti.SEW)>;
+ def : Pat<(vti.Vector (riscv_vle_vl BaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))),
+ (load_instr BaseAddr:$rs1, GPR:$vl, vti.SEW)>;
// Store
- def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), RVVBaseAddr:$rs1,
+ def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), BaseAddr:$rs1,
(XLenVT (VLOp GPR:$vl))),
- (store_instr vti.RegClass:$rs2, RVVBaseAddr:$rs1, GPR:$vl, vti.SEW)>;
+ (store_instr vti.RegClass:$rs2, BaseAddr:$rs1, GPR:$vl, vti.SEW)>;
}
foreach mti = AllMasks in {
defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#mti.BX);
defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#mti.BX);
- def : Pat<(mti.Mask (riscv_vle_vl RVVBaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))),
- (load_instr RVVBaseAddr:$rs1, GPR:$vl, mti.SEW)>;
- def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), RVVBaseAddr:$rs1,
+ def : Pat<(mti.Mask (riscv_vle_vl BaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))),
+ (load_instr BaseAddr:$rs1, GPR:$vl, mti.SEW)>;
+ def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), BaseAddr:$rs1,
(XLenVT (VLOp GPR:$vl))),
- (store_instr VR:$rs2, RVVBaseAddr:$rs1, GPR:$vl, mti.SEW)>;
+ (store_instr VR:$rs2, BaseAddr:$rs1, GPR:$vl, mti.SEW)>;
}
// 12.1. Vector Single-Width Integer Add and Subtract
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