[llvm] 7c749ba - [GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-02-12T21:33:27Z
New Revision: 7c749baa3a26ac4d9b7ee94b93356c3c72714755

URL: https://github.com/llvm/llvm-project/commit/7c749baa3a26ac4d9b7ee94b93356c3c72714755
DIFF: https://github.com/llvm/llvm-project/commit/7c749baa3a26ac4d9b7ee94b93356c3c72714755.diff

LOG: [GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT

There's no need to call verifyVectorElementMatch since we already know
that the source and destination types are identical.

Differential Revision: https://reviews.llvm.org/D96589

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachineVerifier.cpp
    llvm/test/MachineVerifier/test_g_assert_zext.mir
    llvm/test/MachineVerifier/test_g_sext_inreg.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 2691dd8fd89f..ed16ca20acec 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -949,9 +949,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
 
     Register Dst = MI->getOperand(0).getReg();
     Register Src = MI->getOperand(1).getReg();
-    LLT DstTy = MRI->getType(Dst);
     LLT SrcTy = MRI->getType(Src);
-    verifyVectorElementMatch(DstTy, SrcTy, MI);
     int64_t Imm = MI->getOperand(2).getImm();
     if (Imm <= 0) {
       report("G_ASSERT_ZEXT size must be >= 1", MI);
@@ -1398,10 +1396,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
       break;
     }
 
-    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
-    verifyVectorElementMatch(DstTy, SrcTy, MI);
-
     int64_t Imm = MI->getOperand(2).getImm();
     if (Imm <= 0)
       report("G_SEXT_INREG size must be >= 1", MI);

diff  --git a/llvm/test/MachineVerifier/test_g_assert_zext.mir b/llvm/test/MachineVerifier/test_g_assert_zext.mir
index f39be8bf935e..e8dd6910f32a 100644
--- a/llvm/test/MachineVerifier/test_g_assert_zext.mir
+++ b/llvm/test/MachineVerifier/test_g_assert_zext.mir
@@ -19,11 +19,9 @@ body: |
 
    ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT
-   ; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar ***
-   ; CHECK: instruction: %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT
    %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT %0, 8
 
-   ; CHECK: *** Bad machine code: operand types must preserve number of vector elements ***
+   ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT
    %assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT %1, 8
 

diff  --git a/llvm/test/MachineVerifier/test_g_sext_inreg.mir b/llvm/test/MachineVerifier/test_g_sext_inreg.mir
index 387fd2ff35fc..e675a6f37bbb 100644
--- a/llvm/test/MachineVerifier/test_g_sext_inreg.mir
+++ b/llvm/test/MachineVerifier/test_g_sext_inreg.mir
@@ -36,11 +36,9 @@ body: |
 
    ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
-   ; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar ***
-   ; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
    %4(<2 x s32>) = G_SEXT_INREG %0, 8
 
-   ; CHECK: *** Bad machine code: operand types must preserve number of vector elements ***
+   ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %5:gpr(<2 x s32>) = G_SEXT_INREG
    %5(<2 x s32>) = G_SEXT_INREG %1, 8