[llvm] c96e214 - [AMDGPU] Fix Windows build

[Stanislav Mekhanoshin via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2021-02-12T12:30:52-08:00
New Revision: c96e214b9ca7739737cf257baf32ff819854027d

URL: https://github.com/llvm/llvm-project/commit/c96e214b9ca7739737cf257baf32ff819854027d
DIFF: https://github.com/llvm/llvm-project/commit/c96e214b9ca7739737cf257baf32ff819854027d.diff

LOG: [AMDGPU] Fix Windows build

A trivial fix, 64 bit constant is 1ull, not 1ul on Windows.
Fixed build broken by c0d7a8bc6241.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
index faf63fd4edb8..e0ca60bc3023 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -292,7 +292,7 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
     // unused op_sel_hi bits if corresponding operands do not exist.
     // accvgpr_read/write are 
diff erent, however. These are VOP3P, MAI, have
     // src0, but do not use op_sel.
-    Encoding |= (1ul << 14) | (1ul << 59) | (1ul << 60);
+    Encoding |= (1ull << 14) | (1ull << 59) | (1ull << 60);
     break;
   default:
     break;