[PATCH] D96609: [X86][AVX] Truncate vectors with PACKSS/PACKUS on AVX2 targets

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, pengfei, spatel, andreadb.
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Until AVX512 we don't have any vector truncation instructions, and always lower using shuffles instead.

combineVectorTruncation performs this earlier than lowering as it makes it easier to use any sign/zero-extended bits in the truncated bits with PACKSS/PACKUS to perform the shuffle.

We currently don't attempt to use combineVectorTruncation on AVX2 targets as in the past 256-bit PACKSS/PACKUS  tended to cause 128-bit lane shuffle regressions - but these should now be all resolved with combineHorizOpWithShuffle.

We have one remaining regression in psubus.ll that will be addressed by D96413 <https://reviews.llvm.org/D96413> - in all other cases we reduce the amount of cross-lane shuffling and variable shuffle mask usage.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96609

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/masked_store_trunc.ll
  llvm/test/CodeGen/X86/psubus.ll
  llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
  llvm/test/CodeGen/X86/vector-trunc-math.ll
  llvm/test/CodeGen/X86/vector-trunc.ll

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